DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yagnamurthy et al. (U.S 2016/0381800 A1).
As to claim 1, Yagnamurthy et al. disclose in Fig. 1g a semiconductor package, comprising: a substrate (100); a die (104) over the substrate (100) (Fig. 1g, para. [0010]); a molding compound (108) provided over the substrate (100) (Fig. 1g, para. [0011]), wherein the molding compound (108) includes a first groove (“opening” 112) with a first depth (Fig. 1g, para. [0012]) and a second groove (“at least one trench opening” 116) with a second depth (Fig. 1g, para. [0013]), the first depth being different from the second depth (see Fig. 1g).
As to claim 2, as applied to claim 1 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“opening” 112) and the second groove (“at least one trench opening” 116) are located on a top surface of the molding compound (108) (Fig. 1g).
As to claim 3, as applied to claim 1 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“opening” 112) and the second groove (“at least one trench opening” 116) are adjacent to the die (104) (Fig. 1g).
As to claim 4, as applied to claim 1 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the die (104) is a memory die (“memory device”, para. [0010]) (Fig. 1g, para. [0010]).
As to claim 5, as applied to claim 1 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein a total volume of the molding compound (108) in the package (Fig. 1g) is greater than a total volume of the first die (104) in the package (Fig. 1g).
As to claim 6, as applied to claim 1 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the package further comprising a plurality of conductive bumps (“solder balls” 118) located on the substrate (100) (Fig. 1g, para. [0016]).
As to claim 7, Yagnamurthy et al. disclose in Fig. 1g a package, comprising: a substrate (100); a die (104) over the substrate (100) (Fig. 1g, para. [0010]); a molding compound (108) provided over the substrate (100) (Fig. 1g, para. [0011]), wherein the molding compound (108) includes a first groove (“opening” 112) with a first shape and a second groove (“at least one trench opening” 116) with a second shape Fig. 1g, para. [0013]), the first shape being different from the second shape (see Fig. 1g).
As to claim 8, as applied to claim 7 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“opening” 112) and the second groove (“at least one trench opening” 116) are located on a top surface of the molding compound (108) (Fig. 1g).
As to claim 9, as applied to claim 7 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“opening” 112) and the second groove (“at least one trench opening” 116) are adjacent to the die (104) (Fig. 1g).
As to claim 10, as applied to claim 4 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the die (104) is a memory die (“memory device”, para. [0010]) (Fig. 1g, para. [0010]).
As to claim 11, as applied to claim 7 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein a total volume of the molding compound (108) in the package (Fig. 1g) is greater than a total volume of the first die (104) in the package (Fig. 1g).
As to claim 12, as applied to claim 7 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the package further comprising a plurality of conductive bumps (“solder balls” 118) located on the substrate (100) (Fig. 1g, para. [0016]).
As to claim 13, as applied to claim 7 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“opening” 112) with the first shape has a substantially curved bottom surface (Fig. 1g).
As to claim 14, Yagnamurthy et al. disclose in Fig. 1g a package, comprising: a substrate (100); a die (104) over the substrate (100) (Fig. 1g, para. [0010]); a molding compound (108) provided over the substrate (100) (Fig. 1g, para. [0011]), wherein the molding compound (108) includes a first groove (“at least one trench opening” 116) with a first size and a second groove (“opening” 112) with a second size, the first size being different from the second size (Fig. 1g).
As to claim 15, as applied to claim 14 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“at least one trench opening” 116
As to claim 16, as applied to claim 14 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the first groove (“at least one trench opening” 116) and the second groove (“opening” 112) are adjacent to the die (104) (Fig. 1g).
As to claim 17, as applied to claim 14 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein a total volume of the molding compound (108) in the package is greater than a total volume of the first die (104) in the package (Fig. 1g).
As to claim 18, as applied to claim 14 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the package further comprising a plurality of conductive bumps (“solder balls” 118) located on the substrate (100) (Fig. 1g, para. [0016]).
As to claim 19, as applied to claim 14 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations including the limitation: wherein the second groove (“opening” 112) is located near an edge of the molding compound (108) (Fig. 1g).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yagnamurthy et al. (U.S 2016/0381800 A1) in view of Huang et al. (U.S 2016/0079135 A1).
As to claim 20, as applied to claim 14 above, Yagnamurthy et al. disclose in Fig. 1g all claimed limitations except for the package further comprising a passive component disposed on the substrate and overlapped with the first groove.
Huang et al. disclose in Fig. 6 a semiconductor package comprising a passive component (“capacitors” or “resistors”, para. [0015]) disposed on the substrate (102) and overlapped with the first groove (see a groove on “molding compound” 124) (Fig. 6, para. [0015]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the reference of Yagnamurthy et al. by providing a passive component disposed on the substrate as taught by Huang et al., so that the passive component may be overlapped with the first groove of the molding compound, in order to mitigate thermomechanical stress and prevent micro-cracking within the molding compound, so as to improve the reliability of the package.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-9, and 11-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5, 9, 12-13, and 16 of U.S. Patent No. 10,636,715. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited in claims 1-3, 6-9, 12-16, and 18-19 of the present invention are recited within claims 1-2, 5, 9, 12-13, and 16 of the U.S. Patent No. 10,636,715.
Application: 18/761,238
Patent No. US 10,636,715
Claim 1: a semiconductor package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first depth and a second groove with a second depth, the first depth being different from the second depth.
Claims 1 and 5 (and/or claims 12 and 16) recite the limitations of claim 1 of the present invention, the insulating encapsulant has “the vacant groove” and “at least one runner hole opening” that are same as “a first groove” and “a second groove” (as recited in claim 1 of the present invention).
Claim 2: the package according to claim 1, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claims 2 and 5 (and/or claims 13 and 16) recite the limitations of 2 of the present invention, “the vacant groove is located on the second surface” and “at least one runner hole opening located on the second surface of the insulating encapsulant”, the “second surface”/”first surface” is the same as “a top surface” (as recited in claim 2 of the present invention).
Claim 3: the package according to claim 1, wherein the first groove and the second groove are adjacent to the die.
Claims 1 and 5 (and/or claims 12 and 16) recite the limitations of 3 of the present invention, “the insulating encapsulant has a vacant groove that surrounds …the plurality of dies”, and “the plurality of dies are confined to be located within an area surrounded by the vacant groove”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 3 of the present invention).
Claim 5: the package according to claim 1, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claim 1 recites the limitations of claim 5 of the present invention, “the insulating encapsulant has a vacant groove that surrounds the interposer structure and the plurality of dies” which inherently means “a total volume of the molding compound in the package is greater than a total volume of the first die in the package” (as recited in claim 5 of the present invention).
Claim 6: the package according to claim 1, further comprising a plurality of conductive bumps located on the substrate.
Claim 9 (and/or claim 12) recites the limitations of claim 6 of the present invention, “second conductive bumps disposed between the interposer structure and the circuit substrate” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 6 of the present invention).
Claim 7: a package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first shape and a second groove with a second shape, the first shape being different from the second shape.
Claims 1 and 5 recite the limitations of claim 7 of the present invention, the insulating encapsulant has “the vacant groove” and “at least one runner hole opening” have different depths; thus, having different shapes (as recited in claim 7 of the present invention).
Claim 8: the package according to claim 7, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claims 2 and 5 recite the limitations of 8 of the present invention, “the vacant groove is located on the second surface” and “at least one runner hole opening located on the second surface of the insulating encapsulant”, the “second surface” is the same as “a top surface” (as recited in claim 8 of the present invention).
Claim 9: the package according to claim 7, wherein the first groove and the second groove are adjacent to the die.
Claims 1 and 5 recite the limitations of 9 of the present invention, “the insulating encapsulant has a vacant groove that surrounds …the plurality of dies”, and “the plurality of dies are confined to be located within an area surrounded by the vacant groove”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 9 of the present invention).
Claim 11: the package according to claim 7, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claim 1 recites the limitations of claim 11 of the present invention, “the insulating encapsulant has a vacant groove that surrounds the interposer structure and the plurality of dies” which inherently means “a total volume of the molding compound in the package is greater than a total volume of the first die in the package” (as recited in claim 11 of the present invention).
Claim 12: the package according to claim 7, further comprising a plurality of conductive bumps located on the substrate.
Claim 9 (and/or claim 12) recites the limitations of claim 12 of the present invention, “second conductive bumps disposed between the interposer structure and the circuit substrate” which means “a plurality of conductive bumps located on the substrate” (as recited in claim 12 of the present invention).
Claim 13: the package according to claim 7, wherein the first groove with the first shape has a substantially curved bottom surface.
Claim 12 recites the limitations of claim 13 of the present invention, “the insulating encapsulant has a ring shape groove” which include “a shape has a substantially curved bottom surface” (as recited in claim 13 of the present invention).
Claim 14: a package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first size and a second groove with a second size, the first size being different from the second size.
Claims 1 and 5 recite the limitations of claim 14 of the present invention, the insulating encapsulant has “the vacant groove” and “at least one runner hole opening” have different depths; thus, having different sizes (as recited in claim 14 of the present invention).
Claim 15: the package according to claim 14, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claims 2 and 5 (and/or claims 13 and 16) recite the limitations of 2 of the present invention, “the vacant groove is located on the second surface” and “at least one runner hole opening located on the second surface of the insulating
Claim 16: the package according to claim 14, wherein the first groove and the second groove are adjacent to the die.
Claims 1 and 5 recite the limitations of 16 of the present invention, “the insulating encapsulant has a vacant groove that surrounds …the plurality of dies”, and “the plurality of dies are confined to be located within an area surrounded by the vacant groove”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 16 of the present invention).
Claim17: the package according to claim 14, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claim 1 recites the limitations of claim 17 of the present invention, “the insulating encapsulant has a vacant groove that surrounds the interposer structure and the plurality of dies” which inherently means “a total volume of the molding compound in the package is greater than a total volume of the first die in the package” (as recited in claim 17 of the present invention).
Claim 18: the package according to claim 14, further comprising a plurality of conductive bumps located on the substrate.
Claim 9 recites the limitations of claim 18 of the present invention, “second conductive bumps disposed between the interposer structure and the circuit substrate” which means “a plurality of conductive bumps located on the substrate” (as recited in claim 18 of the present invention).
Claim 19: the package according to claim 14, wherein the second groove is located near an edge of the molding compound.
Claim 1 recites the limitations of claim 19 of the present invention, because “the insulating encapsulant has a vacant groove that surrounds …the plurality of dies” and “the plurality of dies are confined to be located within an area surrounded by the vacant groove”; thus, the groove is located near an edge of the molding compound (as recited in claim 19 of the present invention).
Claims 1-3, 5-9, and 11-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 7, 9 of U.S. Patent No. 11,456,226. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited in claims 1-3, 5-9, and 11-19 of the present invention are recited within claims 1, 4, 7, 9 of U.S. Patent No. 11,456,226.
Application: 18/761,238
Patent No. US 11,456,226
Claim 1: a semiconductor package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first depth and a second groove with a second depth, the first depth being different from the second depth.
Claim 1 recites the limitations of claim 1 of the present invention, the insulating encapsulant has “an unfilled groove” and “at least one runner hole opening” that are same as “a first groove” and “a second groove” (as recited in claim 1 of the present invention).
Claim 2: the package according to claim 1, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claim 4 recites the limitations of 2 of the present invention, “the unfilled groove and the at least one runner hole opening are located on the second surface”, the “second surface” is the same as “a top surface” (as recited in claim 2 of the present invention).
Claim 3: the package according to claim 1, wherein the first groove and the second groove are adjacent to the die.
Claim 9 recites the limitations of 3 of the present invention, “the unfilled groove is a ring-shaped groove that is encircling the at least one die, and kept a distance apart from the at least one die”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 3 of the present invention).
Claim 5: the package according to claim 1, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claim 1 recites the limitations of claim 5 of the present invention, “an insulating encapsulant disposed on the circuit substrate and surrounding the at least one die” which inherently means “a total volume of the molding compound in the package is greater than a total volume of the first die in the package” (as recited in claim 5 of the present invention).
Claim 6: the package according to claim 1, further comprising a plurality of conductive bumps located on the substrate.
Claim 7 recites the limitations of claim 6 of the present invention, “conductive bumps disposed in between the at least one die and the circuit substrate” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 6 of the present invention).
Claim 7: a package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first shape and a second groove with a second shape, the first shape being different from the second shape.
Claim 1 recite the limitations of claim 7 of the present invention, the insulating encapsulant has “an unfilled groove” and “at least one runner hole opening” have different depths and thus different shapes (as recited in claim 7 of the present invention).
Claim 8: the package according to claim 7, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claim 4 recites the limitations of 8 of the present invention, “the unfilled groove and the at least one runner hole opening are located on the second surface”, the “second surface” is the same as “a top surface” (as recited in claim 8 of the present invention).
Claim 9: the package according to claim 7, wherein the first groove and the second groove are adjacent to the die.
Claim 9 recites the limitations of 9 of the present invention, “the unfilled groove is a ring-shaped groove that is encircling the at least one die, and kept a distance apart from the at least one die”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 9 of the present invention).
Claim 11: the package according to claim 7, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claim 1 recites the limitations of claim 11 of the present invention, “an insulating encapsulant disposed on the circuit substrate and surrounding the at least one die” which inherently means “a total volume of the molding compound in the package is greater than a total volume of the first die in the package” (as recited in claim 11 of the present invention).
Claim 12: the package according to claim 7, further comprising a plurality of conductive bumps located on the substrate.
Claim 7 recites the limitations of claim 12 of the present invention, “conductive bumps disposed in between the at least one die and the circuit substrate” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 12 of the present invention).
Claim 13: the package according to claim 7, wherein the first groove with the first shape has a substantially curved bottom surface.
Claim 9 recites the limitations of claim 13 of the present invention, “the unfilled groove is a ring-shaped groove” which inherently includes the shape having a substantially curved bottom surface (as recited in claim 13 of the present invention).
Claim 14: a package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first size and a second groove with a second size, the first size being different from the second size.
Claim 1 recite the limitations of claim 14 of the present invention, the insulating encapsulant has “the unfilled groove” and “at least one runner hole opening” have different depths; thus, having different sizes (as recited in claim 14 of the present invention).
Claim 15: the package according to claim 14, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claim 4 recites the limitations of 15 of the present invention, “the unfilled groove and the at least one runner hole opening
are located on the second surface”, the “second surface” is the same as “a top surface” (as recited in claim 15 of the present invention).
Claim 16: the package according to claim 14, wherein the first groove and the second groove are adjacent to the die.
Claim 9 recites the limitations of 16 of the present invention, “the unfilled groove is a ring-shaped groove that is encircling the at least one die, and kept a distance apart from the at least one die”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 16 of the present invention).
Claim 17: the package according to claim 14, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claim 1 recites the limitations of claim 17 of the present invention, “an insulating encapsulant disposed on the circuit substrate and surrounding the at least one die” which inherently means “a total volume of the molding compound in the package is greater than a total volume of the first die in the package” (as recited in claim 17 of the present invention).
Claim 18: the package according to claim 14, further comprising a plurality of conductive bumps located on the substrate.
Claim 7 recites the limitations of claim 18 of the present invention, “conductive bumps disposed in between the at least one die and the circuit substrate” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 18 of the present invention).
Claim 19: the package according to claim 14, wherein the second groove is located near an edge of the molding compound.
Claim 9 recites the limitations of claim 19 of the present invention, “the unfilled groove is a ring-shaped groove that is encircling the at least one die, and kept a distance apart from the at least one die”; thus, the groove is located near an edge of the molding compound (as recited in claim 19 of the present invention).
Claims 1-3, 5-9, and 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4, 7, and 8 of U.S. Patent No. 12,057,359. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited in claims 1-3, 5-9, and 11-20 of the present invention are recited within claims 1-2, 4, 7, and 8 of U.S. Patent No. 12,057,359.
Application: 18/761,238
Patent No. US 12,057,359
Claim 1: a semiconductor package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first depth and a second groove with a second depth, the first depth being different from the second depth.
Claims 1, 4, 7 and 8 recite the limitations of claim 1 of the present invention, “the encapsulant comprises a ring-shaped groove” and “a runner hole opening” that are same as “a first groove” and “a second groove” (as recited in claim 1 of the present invention).
Claim 2: the package according to claim 1, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claim 1 recites the limitations of 2 of the present invention, “a lid structure disposed over the encapsulant and covering the ring-shaped groove” which inherently means “the first groove and the second groove are located on a top surface of the molding compound” (as recited in claim 2 of the present invention).
Claim 3: the package according to claim 1, wherein the first groove and the second groove are adjacent to the die.
Claims 2 and 4 recite the limitations of 3 of the present invention, “wherein the encapsulant surrounds the interposer structure”, and “a plurality of dies disposed on and electrically connected to the interposer structure”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 3 of the present invention).
Claim 5: the package according to claim 1, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claims 2 and 4 recite the limitations of 5 of the present invention, “wherein the encapsulant surrounds the interposer structure”, and “a plurality of dies disposed on and electrically connected to the interposer structure”; thus, the groove and the runner hole opening are inherently adjacent to the die (as recited in claim 5 of the present invention).
Claim 6: the package according to claim 1, further comprising a plurality of conductive bumps located on the substrate.
Claim 2 recites the limitations of claim 6 of the present invention, “an interposer structure disposed on and electrically connected to the substrate through a plurality of conductive bumps” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 6 of the present invention).
Claim 7: a package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first shape and a second groove with a second shape, the first shape being different from the second shape.
Claims 1, 4, 7, and 8 recite the limitations of claim 7 of the present invention, the insulating encapsulant has “ring-shaped groove” and “at least one runner hole opening” have different depths; thus, having different shapes (as recited in claim 7 of the present invention).
Claim 8: the package according to claim 7, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claim 1 recites the limitations of 8 of the present invention, “a lid structure disposed over the encapsulant and covering the ring-shaped groove” which inherently means “the first groove and the second groove are located on a top surface of the molding compound” (as recited in claim 8 of the present invention).
Claim 9: the package according to claim 7, wherein the first groove and the second groove are adjacent to the die.
Claims 2 and 4 recite the limitations of 9 of the present invention, “wherein the encapsulant surrounds the interposer structure”, and “a plurality of dies disposed on and electrically connected to the interposer structure”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 9 of the present invention).
Claim 11: the package according to claim 7, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claims 2 and 4 recite the limitations of 11 of the present invention, “wherein the encapsulant surrounds the interposer structure”, and “a plurality of dies disposed on and electrically connected to the interposer structure”; thus, the groove and the runner hole opening are inherently adjacent to the die (as recited in claim 11 of the present invention).
Claim 12: the package according to claim 7, further comprising a plurality of conductive bumps located on the substrate.
Claim 2 recites the limitations of claim 12 of the present invention, “an interposer structure disposed on and electrically connected to the substrate through a plurality of conductive bumps” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 12 of the present invention).
. Claim 13: the package according to claim 7, wherein the first groove with the first shape has a substantially curved bottom surface.
Claim 1 recites the limitations of claim 13 of the present invention, “the encapsulant comprises a ring-shaped groove” which inherently includes “a shape has a substantially curved bottom surface” (as recited in claim 13 of the present invention).
Claim 14: a package, comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove with a first size and a second groove with a second size, the first size being different from the second size.
Claims 1, 4, 7 and 8 recite the limitations of claim 14 of the present invention, “the encapsulant comprises a ring-shaped groove” and “a runner hole opening” that have different depths; thus, having different sizes (as recited in claim 14 of the present invention).
Claim 15: the package according to claim 14, wherein the first groove and the second groove are located on a top surface of the molding compound.
Claim 1 recites the limitations of 15 of the present invention, “a lid structure disposed over the encapsulant and covering the ring-shaped groove” which inherently means “the first groove and the second groove are located on a top surface of the molding compound” (as recited in claim 15 of the present invention).
Claim 16: the package according to claim 14, wherein the first groove and the second groove are adjacent to the die.
Claim 9 recites the limitations of 16 of the present invention, “the unfilled groove is a ring-shaped groove that is encircling the at least one die, and kept a distance apart from the at least one die”; thus, the groove and the runner hole opening are adjacent to the die (as recited in claim 16 of the present invention).
Claim 17: the package according to claim 14, wherein a total volume of the molding compound in the package is greater than a total volume of the first die in the package.
Claims 2 and 4 recite the limitations of 17 of the present invention, “wherein the encapsulant surrounds the interposer structure”, and “a plurality of dies disposed on and electrically connected to the interposer structure”; thus, the groove and the runner hole opening are inherently adjacent to the die (as recited in claim 17 of the present invention).
Claim 18: the package according to claim 14, further comprising a plurality of conductive bumps located on the substrate.
Claim 2 recites the limitations of claim 18 of the present invention, “an interposer structure disposed on and electrically connected to the substrate through a plurality of conductive bumps” which inherently means “a plurality of conductive bumps located on the substrate” (as recited in claim 18 of the present invention).
Claim 19: the package according to claim 14, wherein the second groove is located near an edge of the molding compound.
Claim 2 recites the limitations of claim 19 of the present invention, “wherein the encapsulant surrounds the interposer structure, and the ring-shaped groove is kept a distance apart from the interposer structure”; thus, the groove is inherently located near an edge of the molding compound (as recited in claim 19 of the present invention).
Claim 20: the package according to claim 14, further comprising a passive component disposed on the substrate and overlapped with the first groove.
Claim 1 recites the limitations of claim 20 of the present invention, “wherein the encapsulant comprises a ring-shaped groove that is overlapped with the plurality of passive component”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kim et al. (US 20150123290 A1), JANG et al. (US 20140339708 A1), Hong et al. (US 20130187288 A1), Lee et al. (US 20110233747 A1), GERBER (US 20100072600 A1), Yeh et al. (US 20170317041 A1), GANESAN et al. (US 20160284642 A), and Chung (US 8546932 B1) disclose a semiconductor package comprising: a substrate; a die over the substrate; a molding compound provided over the substrate, wherein the molding compound includes a first groove and a second groove.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817 August 8, 2026
Prosecution Insights