DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 11/27/2025.
Claims 1-20 are pending in this application.
Applicant made a provisional election to prosecute the invention of Group I, claims 1-14, is acknowledged.
Because Applicant did not distinctly and specifically point out the supposed error in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claims 15-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 07/02/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kurosawa et al. (US 2006/0175697)
Regarding claim 1, Kurosawa discloses a die stack structure, comprising:
a first die 12-2 (see fig. 124);
an encapsulant 10 laterally wrapping around the first die 12-2;
a second die 12-1, disposed below the first die 12-2 and electrically connected with the first die 12-2 (via electrodes 55-1, 55-2 and stud bumps 56-1, 56-2), wherein the second die 12-1 (or die 12, which is shown upside down in figs. 146B, 147B) comprises a body portion having a top surface (bottom surface in figs. 146b, 147B), a bottom surface (top surface), a first side surface (front side surface), a second side surface (back side surface) and a curved side surface (right side surface), the curved side surface is between the first side surface and the second side surface, the curved side surface connects the first side surface and the second side surface, and the first side surface, the second side surface and the curved side surface all connect the top surface and the bottom surface; and
a redistribution layer 11, disposed below the second die 12-1 and electrically connected with the second die 12-1 (via electrode 55-1 and stud bump 56-1).
Regarding claim 2, Kurosawa discloses the die stack structure according to claim 1, wherein the encapsulant 10 laterally wraps around the second die 12-1 and is in contact with the redistribution layer 11. See fig. 124.
Regarding claim 3, Kurosawa discloses the die stack structure according to claim 1, wherein the encapsulant 10 is in contact with the redistribution layer 11. See fig. 124.
Regarding claim 4, Kurosawa discloses the die stack structure according to claim 1, wherein the bottom surface of the body portion 12-1 (including die attach film 13-1) is in contact with the redistribution layer 11. See fig. 124.
Regarding claim 5, Kurosawa discloses the die stack structure according to claim 1, wherein the top surface of the body portion 12-1 (including semiconductor element 19; see figs. 124, 125, and para. 0327) is in contact with the first die.
Regarding claim 6, Kurosawa discloses the die stack structure according to claim 1, wherein the body portion comprises a semiconductor substrate 12, an interconnect structure disposed on the semiconductor substrate, and a bonding structure 15-2A disposed on the interconnect structure. See figs. 1, 2.
Regarding claim 7, Kurosawa discloses the die stack structure according to claim 6, wherein the body portion comprises through semiconductor vias embedded in the 2semiconductor substrate and electrically connected with the interconnect structure. See figs. 124, 126, 165.
Regarding claim 8, Kurosawa discloses a die stack structure, comprising:
a first die 12-2 (see fig. 124);
an encapsulant 10 laterally wrapping around the first die 12-2;
a second die 12-1, disposed below the first die 12-2 and electrically connected with the first die 12-2 (via electrodes 55-1, 55-2 and stud bumps 56-1, 56-2), wherein the second die 12-1 (or die 12, which is shown upside down in figs. 146B, 147B) comprises a body portion having a top surface (bottom surface in figs. 146b, 147B), a bottom surface (top surface), a first side surface (front side surface), a second side surface (right side surface) and a third side surface (back side surface), the top surface and the bottom surface are connected with the first side surface, the second side surface and the third side surface, the second side surface (right side surface) located between the first and third side surfaces (front and back side surfaces, respectively) connects the first side surface and the third side surface,
a first obtuse angle (see figs. 140A/B, 140A/B) is included between the first side surface (front side surface) and the second side surface (right side surface), and a second obtuse angle is included between the second side surface (right side surface) and the third side surface (back side surface); and
a redistribution layer 11 (fig. 124), disposed below the second die 12-1 and electrically connected with the second die 12-1 (via electrode 55-1 and stud bump 56-1).
Regarding claim 9, Kurosawa discloses the die stack structure according to claim 8, wherein the top surface of the body portion 12-1 (including semiconductor element 19; see figs. 124, 125, and para. 0327) is in contact with the first die.
Regarding claim 10, Kurosawa discloses the die stack structure according to claim 8, wherein an outer profile of the encapsulant 10 is vertically aligned with an outer profile of the redistribution layer 11. See fig. 124.
Regarding claim 11, Kurosawa discloses the die stack structure according to claim 10, wherein the encapsulant 10 is in contact with the entire second side surface. See fig. 124.
Regarding claim 12, Kurosawa discloses the die stack structure according to claim 8, wherein the body portion comprises a semiconductor substrate 12, an interconnect structure disposed on the semiconductor substrate, and a bonding structure 15-2A disposed on the interconnect structure. See figs. 1, 2.
Regarding claim 13, Kurosawa discloses the die stack structure according to claim 12, wherein the semiconductor substrate, the interconnect structure and the bonding structure have the second side surface. See figs. 124, 140, 146, 147.
Regarding claim 14, Kurosawa discloses the die stack structure according to claim 13, wherein the semiconductor substrate is in contact with the redistribution layer 11, and the bonding structure is in contact with the first die. See figs. 124, 148.
Conclusion
6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 January 10, 2026