DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, directed to claims 9-16 in the reply filed on August 11, 2026 is acknowledged. Claims 1-8 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Currently, claims 9-16 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kellar et al. (US 2004/0014308 A1; hereafter Kellar ‘308) in view of Kellar et al. (US 2003/0148596 A1; hereafter Kellar ‘596).
Regarding claim 9, Kellar ‘308 teaches a semiconductor device (see e.g., 4-wafer vertical stack 300, Figure 3), comprising:
a first stack structure comprising:
a first wafer bonded to a second wafer (see e.g., first wafer stack includes wafers 310 and 320 bonded via a metal bonding layer 106 deposited on opposing surfaces of the wafers 310 and 320 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 310 and 320 and to bond the adjacent wafers 310 and 320 while maintain electrical isolation between bonding areas via an ILD layer 108, Para [0028], Figure 3);
a second stack structure bonded to the first stack structure (see e.g., second wafer stack including wafers 330 and 340 bonded to the first wafer stack via vertical vias 324, Para [0028], Figure 3), wherein the second stack structure comprises:
a third wafer bonded to a fourth wafer (see e.g., second wafer stack includes wafers 330 and 340 bonded via the same metal bonding layer 106 deposited on opposing surfaces of the wafers 330 and 340 at designated bonding areas to establish electrical connections between active IC devices on adjacent wafers 330 and 340 and to concurrently bond the adjacent wafers 330 and 340, while maintaining electrical isolation between bonding areas via an ILD layer 108, Para [0028], Figure 3);
Kellar ‘308 does not explicitly teach
“first bumps on a top surface of the first stack structure; and
second bumps on a bottom surface of the second stack structure and directly connected to the first bumps”.
Kellar ‘308 recognizes that the use of inter-wafer vias for bonding the first wafer stack and the second wafer stack may cause increased resistance capacitance (RC) delay in the active IC devices and suggests that alternative interconnection techniques may be employed.
In a similar field of endeavor Kellar ‘596 teaches an alternative interconnection arrangement in which conductive bumps are provided on opposing surfaces of vertically adjacent semiconductor structures (see e.g., Figure 2) and corresponding bumps are directly bonded to one another thereby providing electrical and mechanical connection between the semiconductor structures.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Kellar ‘596 ‘s teachings of replacing the inter-wafer via connection between the first and second stack structures with the opposing bump to bump connection in the device of Kellar ‘308 to reduce interconnect RC delay while maintaining electrical and mechanical connection between the vertically stacked semiconductor structures. Such a modification would have involved the substitution of one known vertical interconnection technique for another known interconnection technique to obtain the predictable result of electrically and mechanically connecting the first and second stack structures.
Regarding claim 10, Kellar ‘308, as modified by Kellar ‘596, teaches the limitations of claim 9 as mentioned above. Kellar ‘308 further teaches
further comprising:
first direct bond interconnects (DBIs) in the first wafer;
second DBIs in the second wafer (see e.g., metal bonding layer 106 including a plurality of copper lines formed at opposing surfaces of the wafers 310 and 320, that directly bond and electrically interconnect the wafers 310 and 320 to form a first bonded wafer stack, Paras [0027], [0028], Figure 3);
third DBIs in the third wafer; and
fourth DBIs in the fourth wafer (see e.g., metal bonding layer 106 including a plurality of copper lines formed at opposing surfaces of the wafers 330 and 340, that directly bond and electrically interconnect the wafers 330 and 340 to form a first bonded wafer stack, Paras [0027], [0028], Figure 3).
Regarding claim 11, Kellar ‘308, as modified by Kellar ‘596, teaches the limitations of claim 10 as mentioned above. Kellar ‘308 further teaches
wherein the first DBIs are directly connected to the second DBIs (see e.g., metal bonding layer 106 including a plurality of copper lines formed at opposing surfaces of the wafers 310 and 320, that directly bond and electrically interconnect the wafers 310 and 320 to form a first bonded wafer stack, Paras [0027], [0028], Figure 3).
Regarding claim 12, Kellar ‘308, as modified by Kellar ‘596, teaches the limitations of claim 10 as mentioned above. Kellar ‘308 further teaches
wherein the third DBIs are directly connected to the fourth DBIs (see e.g., metal bonding layer 106 including a plurality of copper lines formed at opposing surfaces of the wafers 330 and 340, that directly bond and electrically interconnect the wafers 330 and 340 to form a first bonded wafer stack, Paras [0027], [0028], Figure 3).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kellar et al. (US 2004/0014308 A1; hereafter Kellar ‘308) in view of Kellar et al. (US 2003/0148596 A1; hereafter Kellar ‘596) and further in view of Shih et al. (US 2020/0402891 A1; hereafter Shih).
Regarding claim 13, Kellar ‘308, as modified by Kellar ‘596, teaches the limitations of claim 9 as mentioned above. Kellar ‘308 does not explicitly teach
“further comprising:
a third stack structure bonded to the second stack structure, wherein the third stack structure comprises:
a fifth wafer bonded to a sixth wafer;
third bumps on a top surface of the second stack structure; and
fourth bumps on a bottom surface of the third stack structure and directly connected to the third bumps”.
In a similar field of endeavor Shih teaches
further comprising:
a third stack structure bonded to the second stack structure, wherein the third stack structure comprises:
a fifth wafer bonded to a sixth wafer;
third bumps on a top surface of the second stack structure; and
fourth bumps on a bottom surface of the third stack structure and directly connected to the third bumps (see e.g., Figure 2 teaches a plurality of two wafer stack structures. A third structure 300 comprising wafers 1301 and 1302 bonded together in addition to first and second two wafer structures 100’ and 200’. Metal bumps 306 disposed at the interface between the preceding stacked structures 100’/200’ and the third structure 300 electrically connect the stack structures, Paras [0041], [0042], Figure 2).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Shih’s teachings of further comprising: a third stack structure bonded to the second stack structure, wherein the third stack structure comprises: a fifth wafer bonded to a sixth wafer; third bumps on a top surface of the second stack structure; and fourth bumps on a bottom surface of the third stack structure and directly connected to the third bumps in the device of Kellar ‘308 in order to increase the number of vertically integrated semiconductor structures and thereby increase integration density while employing the known modular stack and bump interconnection arrangement.
Regarding claim 15, Kellar ‘308, as modified by Kellar ‘596 and Shih, teaches the limitations of claim 13 as mentioned above. Kellar ‘308 does not explicitly teach
“further comprising:
a fourth stack structure bonded to the third stack structure, wherein the fourth stack structure comprises:
a seventh wafer bonded to an eighth wafer;
fifth bumps on a top surface of the third stack structure; and
sixth bumps on a bottom surface of the fourth stack structure and directly connected to the fifth bumps”.
In a similar field of endeavor Shih teaches
further comprising:
a fourth stack structure bonded to the third stack structure, wherein the fourth stack structure comprises:
a seventh wafer bonded to an eighth wafer;
fifth bumps on a top surface of the third stack structure; and
sixth bumps on a bottom surface of the fourth stack structure and directly connected to the fifth bumps (see e.g., Figure 2 teaches a plurality of two wafer stack structures. A fourth structure 400 comprising wafers 1401 and 1402 bonded together in addition to first, second and third two wafer structures 100’, 200’ and 300. Metal bumps 206 disposed at the interface between the preceding stacked structures 100’/200’/300 and the fourth structure 400 electrically connect the stack structures, Paras [0041], [0042], Figure 2).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Shih’s teachings of further comprising: a fourth stack structure bonded to the third stack structure, wherein the fourth stack structure comprises: a seventh wafer bonded to an eighth wafer; fifth bumps on a top surface of the third stack structure; and sixth bumps on a bottom surface of the fourth stack structure and directly connected to the fifth bumps in the device of Kellar ‘308 in order to increase the number of vertically integrated semiconductor structures and thereby increase integration density while employing the known modular stack and bump interconnection arrangement.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kellar et al. (US 2004/0014308 A1; hereafter Kellar ‘308) in view of Kellar et al. (US 2003/0148596 A1; hereafter Kellar ‘596) and Shih et al. (US 2020/0402891 A1; hereafter Shih) and further in view of Chen et al. (US 2022/0278074 A1; hereafter Chen).
Regarding claim 14, Kellar ‘308, as modified by Kellar ‘596 and Shih, teaches the limitations of claim 13 as mentioned above. Kellar ‘308 does not explicitly teach
“further comprising:
fifth DBIs in the fifth wafer; and
sixth DBIs in the sixth wafer”.
In a similar field of endeavor Chen teaches
further comprising:
fifth DBIs in the fifth wafer; and
sixth DBIs in the sixth wafer (see e.g., Figure 30 teaches a two-layer wafer stack 300 comprising a first wafer 200a and a second wafer 200b bonded together by hybrid bonding. The hybrid bonding technique is described with respect to Figure 20A wherein corresponding conductive features including bond pad 255 and via 120 are directly bonded by a direct metal to metal bond without an intervening bonding material.
Such two-layer wafer stacks may be repeatedly added to form a multilayer wafer structure as shown in Figure 32, thereby demonstrating the repeated use of the same direct bond two wafer stack architecture, Paras [0055] – [0056], Figures 30-32).
Therefore, it would have been obvious to ne skilled in art at the time the invention was effectively filed to implement Chen’s teachings of fifth DBIs in the fifth wafer; and sixth DBIs in the sixth wafer in the device of Kellar ‘308 to provide electrical and mechanical interconnection between the wafers of the additional stack structure.
Regarding claim 16, Kellar ‘308, as modified by Kellar ‘596 and Shih, teaches the limitations of claim 15 as mentioned above. Kellar ‘308 does not explicitly teach
“further comprising:
seventh DBIs in the seventh wafer; and
eighth DBIs in the eighth wafer”.
In a similar field of endeavor Chen teaches
further comprising:
seventh DBIs in the seventh wafer; and
eighth DBIs in the eighth wafer (see e.g., Figure 30 teaches a two-layer wafer stack 300 comprising a first wafer 200a and a second wafer 200b bonded together by hybrid bonding. The hybrid bonding technique is described with respect to Figure 20A wherein corresponding conductive features including bond pad 255 and via 120 are directly bonded by a direct metal to metal bond without an intervening bonding material.
Such two-layer wafer stacks may be repeatedly added to form a multilayer wafer structure as shown in Figure 32, thereby demonstrating the repeated use of the same direct bond two wafer stack architecture, Paras [0055] – [0056], Figures 30-32).
Therefore, it would have been obvious to ne skilled in art at the time the invention was effectively filed to implement Chen’s teachings of seventh DBIs in the seventh wafer; and eighth DBIs in the eighth wafer in the device of Kellar ‘308 to provide electrical and mechanical interconnection between the wafers of the additional stack structure.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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