DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, directed to claims 1-16 and added new claims 21-24 in the reply filed on August 24, 2026 is acknowledged. Claims 17-20 have been cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 13-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claims 3 and 13, the limitation, “removing the gate structure to form a recess in the dielectric layer, wherein the recess exposes first portions of the first semiconductor material and second portions of the second semiconductor material”, renders the scope of the claimed process unclear.
It is unclear whether the removal of gate structure itself directly exposes the first and second semiconductor materials or whether an intermediate material removal step is required.
The claim subsequently recites “after removing the gate structure, selectively removing the first portions of the first semiconductor material, wherein after the selectively removing, the second portions of the second semiconductor material remain to form a plurality of nanostructures”, further obscures the relationship between the gate removal step, exposure of the first and second semiconductor materials and the subsequent selective removal step.
Accordingly, it is unclear at what stage the recited first and second portions become exposed and what structural portions are encompassed by the recited “first portions” and “second portions”.
Claims 14-16 depend upon claim 13 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang).
Regarding claim 1, More teaches a method of forming a semiconductor device (see e.g., Figures 1-11), the method comprising:
forming a fin structure that protrudes above a substrate (see e.g., fin structure 108 protruding from the substrate 106, Para [0022], Figure 2C), wherein the fin structure comprises a fin and a layer stack overlying the fin (see e.g., fin structure 108 includes a fin base 108A and fin top portion 108B with a stack of semiconductor layers, Paras [0022], ]0024], Figure 2C), wherein the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material (see .g., fin top portion 108B includes a first group of semiconductor layers 122 and a second group of semiconductor layers 124 stacked in an alternating configuration. Each semiconductor layer 122 and 124 can be epitaxially grown on its underlying layer and can include semiconductor materials different from each other. Each of the semiconductor layers 122 can be formed of silicon and each of semiconductor layers 124 can be formed of silicon germanium (SiGe), Para [0024], Figure 2C);
forming a gate structure over the fin structure (see e.g., polysilicon gate structures 112 formed over the fin 108, Para [0027], Figures 3A-3b);
forming source/drain openings in the fin structure on opposing sides of the gate structure (see e.g., recesses 402 formed in the substrate 106 and between adjacent polysilicon gate structures 112, Para [0029], Figure 4);
replacing first end portions of the first semiconductor material exposed by the source/drain openings with inner spacers (see e.g., portions of semiconductor layers 124 can be etched back to form recessed regions and dielectric material can be deposited in the recessed regions to form inner spacers 127 for an NMOS device, Paras [0030], [0031], Figure 5);
……forming source/drain regions in the source/drain openings (see e.g., source/drain regions including epitaxial end caps 702, epitaxial base 704 and second epitaxial layer 806 formed in the source/drain openings, Paras [0038], [0042], [0044], Figures 7-8).
More does not explicitly teach
“after the replacing, performing an ion implantation process, wherein the ion implantation process implants a first dopant into second end portions of the second semiconductor material exposed by the source/drain openings; and
after performing the ion implantation process, forming source/drain regions in the source/drain openings.”
In a similar field of endeavor Zhang teaches
after the replacing, performing an ion implantation process (see e.g., one or more implantation process may be performed whereby ions 133 are directed into the GAA stack 102, after formation of the S/D cavity 130 and inner spacer 134, Para [0032], Figure 1), wherein the ion implantation process implants a first dopant into second end portions of the second semiconductor material exposed by the source/drain openings; and (see e.g., the ions 133 may include p-type or n-type species depending on whether the GAA stack 102 is an nGAA stack or a pGAA stack. The ions are directed into the exposed surfaces of the GAA stack 102 that is, channels 106 at a non-zero angle (θ) relative to a plane (y-z plane) defined by an exterior surface of the GAA stack 102 within the S/D cavity 130, Para [0032], Figure 1)
after performing the ion implantation process, forming source/drain regions in the source/drain openings (see e.g., next, a S/D material 135 is epitaxially formed within the S/D cavities 130 to form S/D 136, Para [0034], Figure 2).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Zhang’s teachings of after the replacing, performing an ion implantation process, wherein the ion implantation process implants a first dopant into second end portions of the second semiconductor material exposed by the source/drain openings; and after performing the ion implantation process, forming source/drain regions in the source/drain openings in the method of More to provide controlled and more uniform doping of the exposed nanosheet channel regions.
Regarding claim 2, More, as modified by Zhang, teaches the limitations of claim 1 as mentioned above. More further teaches
further comprising, after forming the source/drain regions:
forming a dielectric layer over the source/drain regions around the gate structure; and (see e.g., interlayer dielectric (ILD) layer 1118 disposed on the source/drain regions and between spacers 114 of the polysilicon gate structures 112, Paras [0049], [0050], Figure 11)
replacing the gate structure with a replacement gate structure (see e.g., the gate structure is replaced by metal gate structures including gate dielectric layers 1112, work function layers 1114 and gate electrodes 1116, Paras [0049], [0051], [0052], Figure 11).
Regarding claim 3, More, as modified by Zhang, teaches the limitations of claim 2 as mentioned above. More further teaches
wherein replacing the gate structure comprises:
removing the gate structure to form a recess in the dielectric layer (see e.g., the polysilicon gate structures are replaced by metal gate structures. The formation of ILD layer 1118 is followed by forming a recess by removing the polysilicon gate structures 112, Paras [0049], [0051], Figure 11), wherein the recess exposes first portions of the first semiconductor material and second portions of the second semiconductor material (see e.g., recess formed by removing the polysilicon gate structure 112 exposes the semiconductor layers, Figure 11);
after removing the gate structure, selectively removing the first portions of the first semiconductor material, wherein after the selectively removing, the second portions of the second semiconductor material remain to form a plurality of nanostructures (see e.g., semiconductor layers 124 are selectively removed exposing semiconductor layers 122 referred to as nanostructures, Para [0051], Figure 11);
forming a gate dielectric material around the plurality of nanostructures; and (see e.g., gate dielectric layers 1112 formed around the semiconductor layers 122, Para [0051], Figure 11)
forming a gate electrode material around the gate dielectric material (see e.g., forming work function layer 1114 and gate electrode 1116 around the gate dielectric 1112, Paras [0051], [0052], Figure 11).
Regarding claim 12, More teaches a method of forming a semiconductor device (see e.g., Figures 1-11), the method comprising:
forming a fin structure that protrudes above a substrate (see e.g., fin structure 108 protruding from the substrate 106, Para [0022], Figure 2C), wherein the fin structure comprises a fin and alternating layers of a first semiconductor material and a second semiconductor material over the fin (see e.g., fin structure 108 includes a fin base 108A and fin top portion 108B with a stack of semiconductor layers including a first group of semiconductor layers 122 and a second group of semiconductor layers 124 stacked in an alternating configuration. Each semiconductor layer 122 and 124 can be epitaxially grown on its underlying layer and can include semiconductor materials different from each other. Each of the semiconductor layers 122 can be formed of silicon and each of semiconductor layers 124 can be formed of silicon germanium (SiGe), Paras [0022], ]0024], Figure 2C);
forming a dummy gate structure over the fin structure (see e.g., polysilicon gate structures 112 formed over the fin 108, Para [0027], Figures 3A-3b);
forming source/drain openings in the fin structure on opposing sides of the dummy gate structure (see e.g., recesses 402 formed in the substrate 106 and between adjacent polysilicon gate structures 112, Para [0029], Figure 4);
forming inner spacers between adjacent layers of the second semiconductor material (see e.g., portions of semiconductor layers 124 can be etched back to form recessed regions and dielectric material can be deposited in the recessed regions to form inner spacers 127 for an NMOS device, Paras [0030], [0031], Figure 5);
….. forming source/drain regions in the source/drain openings (see e.g., source/drain regions including epitaxial end caps 702, epitaxial base 704 and second epitaxial layer 806 formed in the source/drain openings, Paras [0038], [0042], [0044], Figures 7-8), wherein the source/drain regions are formed to have a second dopant (see e.g., the first epitaxial layer 602 etched back to form the epitaxial end caps 702 on end portions of the semiconductor layers 122 and epitaxial base 704 in recesses 402, and the second epitaxial layer 806 are both doped with either p-type or n-type dopants to support PMOS or NMOS configurations, Paras [0037], [0038], [0045], Figures 8 and 10);
forming a dielectric layer around the dummy gate structure; and (see e.g., interlayer dielectric (ILD) layer 1118 disposed on the source/drain regions and between spacers 114 of the polysilicon gate structures 112, Paras [0049], [0050], Figure 11)
replacing the dummy gate structure with a replacement gate structure (see e.g., the gate structure is replaced by metal gate structures including gate dielectric layers 1112, work function layers 1114 and gate electrodes 1116, Paras [0049], [0051], [0052], Figure 11).
More does not explicitly teach
“after forming the inner spacers, implanting a first dopant into end portions of the second semiconductor material exposed by the source/drain openings;
after implanting the first dopant, forming source/drain regions in the source/drain openings;”
In a similar field of endeavor Zhang teaches
after forming the inner spacers, implanting a first dopant into end portions of the second semiconductor material exposed by the source/drain openings (see e.g., one or more implantation process may be performed whereby ions 133 are directed into the GAA stack 102, after formation of the S/D cavity 130 and inner spacer 134. The ions 133 may include p-type or n-type species depending on whether the GAA stack 102 is an nGAA stack or a pGAA stack. The ions are directed into the exposed surfaces of the GAA stack 102 that is, channels 106 at a non-zero angle (θ) relative to a plane (y-z plane) defined by an exterior surface of the GAA stack 102 within the S/D cavity 130, Para [0032], Figure 1);
after implanting the first dopant, forming source/drain regions in the source/drain openings.. (see e.g., next, a S/D material 135 is epitaxially formed within the S/D cavities 130 to form S/D 136, Para [0034], Figure 2);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Zhang’s teachings of after forming the inner spacers, implanting a first dopant into end portions of the second semiconductor material exposed by the source/drain openings; after implanting the first dopant, forming source/drain regions in the source/drain openings.. in the method of More to provide controlled and more uniform doping of the exposed nanosheet channel regions.
Regarding claim 13, More, as modified by Zhang, teaches the limitations of claim 12 as mentioned above. More further teaches
wherein replacing the dummy gate structure comprises:
removing the dummy gate structure to form a recess in the dielectric layer (see e.g., the polysilicon gate structures are replaced by metal gate structures. The formation of ILD layer 1118 is followed by forming a recess by removing the polysilicon gate structures 112, Paras [0049], [0051], Figure 11), wherein the recess exposes first portions of the first semiconductor material and second portions of the second semiconductor material (see e.g., recess formed by removing the polysilicon gate structure 112 exposes the semiconductor layers, Figure 11);
after removing the dummy gate structure, selectively removing the first portions of the first semiconductor material, wherein after the selectively removing, the second portions of the second semiconductor material remain to form nanostructures (see e.g., semiconductor layers 124 are selectively removed exposing semiconductor layers 122 referred to as nanostructures, Para [0051], Figure 11);
forming a gate dielectric material around the nanostructures; and (see e.g., gate dielectric layers 1112 formed around the semiconductor layers 122, Para [0051], Figure 11)
forming a gate electrode material around the gate dielectric material (see e.g., forming work function layer 1114 and gate electrode 1116 around the gate dielectric 1112, Paras [0051], [0052], Figure 11).
Claims 4 and 14 rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang) and further in view of Frougier et al. (US 2023/0142410 A1; hereafter Frougier).
Regarding claim 4, More, as modified by Zhang, teaches the limitations of claim 1 as mentioned above. More does not explicitly teach
“wherein the source/drain openings are formed to have sloped sidewalls such that a width of the source/drain openings decreases as the source/drain openings extend toward the substrate”.
In a similar field of endeavor Frougier teaches
wherein the source/drain openings are formed to have sloped sidewalls such that a width of the source/drain openings decreases as the source/drain openings extend toward the substrate (see e.g., source/drain recess is defined by sloped sidewalls such that the width of the opening decreases towards the substrate 105. The nano stack 102 is etched along the X-axis (i.e., cross section A) to taper the length of the nano stack 102. The taper of the nano stack 102 is such that each layer is progressively longer when going from the top layer to the bottom layer (e.g, the seventh layer 140 to the second layer 115). For example, the third layer 120 has a length L.sub.1, the fifth layer 130 has a length L.sub.2, and the seventh layer has a length L.sub.3. The nano stack 102 is tapered so that L.sub.1>L.sub.2>L.sub.3, Para [0052], Figures 12, 14 and 16)
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Frougier’s teachings of wherein the source/drain openings are formed to have sloped sidewalls such that a width of the source/drain openings decreases as the source/drain openings extend toward the substrate in the method of More to obtain a controlled source/drain recess profile suitable for subsequent inner spacer and source/drain formation.
Regarding claim 14, More, as modified by Zhang, teaches the limitations of claim 1 as mentioned above. More does not explicitly teach
“wherein the nanostructures are formed to have opposing sloped sidewalls facing the source/drain regions,
wherein a length of the nanostructures, measured between the opposing sloped sidewalls of the nanostructures, increases along a depth direction of the source/drain openings toward the substrate”.
In a similar field of endeavor Frougier teaches
wherein the nanostructures are formed to have opposing sloped sidewalls facing the source/drain regions,
wherein a length of the nanostructures, measured between the opposing sloped sidewalls of the nanostructures, increases along a depth direction of the source/drain openings toward the substrate (see e.g., source/drain recess is defined by sloped sidewalls such that the width of the opening decreases towards the substrate 105. The nano stack 102 is etched along the X-axis (i.e., cross section A) to taper the length of the nano stack 102. The taper of the nano stack 102 is such that each layer is progressively longer when going from the top layer to the bottom layer (e.g, the seventh layer 140 to the second layer 115). For example, the third layer 120 has a length L.sub.1, the fifth layer 130 has a length L.sub.2, and the seventh layer has a length L.sub.3. The nano stack 102 is tapered so that L.sub.1>L.sub.2>L.sub.3, Para [0052], Figures 12, 14 and 16)
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Frougier’s teachings of wherein the nanostructures are formed to have opposing sloped sidewalls facing the source/drain regions, wherein a length of the nanostructures, measured between the opposing sloped sidewalls of the nanostructures, increases along a depth direction of the source/drain openings toward the substrate in the method of More to obtain a controlled source/drain recess profile suitable for subsequent inner spacer and source/drain formation.
Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang) and Frougier et al. (US 2023/0142410 A1; hereafter Frougier) and further in view of Lin et al. (US 2022/0037465 A1; hereafter Lin) and Shin et al. (US 2020/0365586 A1; hereafter Shin).
Regarding claim 5, More, as modified by Zhang and Frougier, teaches the limitations of claim 4 as mentioned above. More does not explicitly teach
“wherein the first dopant is implanted into the second end portions of the second semiconductor material to form doped regions in the second semiconductor material, wherein a concentration of the first dopant in the doped regions increases along a depth direction of the source/drain openings toward the substrate”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Lin teaches doped channel junction regions 58A, 58B and 58C formed in the end portions of vertically stacked channel layers 54A, 54B and 54C. Figure 15B shows the lateral straggling of the doped channel junction regions increases toward the substrate such that the lower doped channel junction region extends farther into the channel than the vertically higher doped channel junction region.
Lin further teaches that the lateral straggling, ion concentration and dopant species of each doped channel junction region may be independently selected to obtain a desired junction characteristics and reduce channel resistance (see e.g., Paras [0059], [0108]).
While Lin teaches the lateral straggling of the doped channel junction regions increases toward the substrate, Lin does not explicitly teach the dopant concentration itself likewise increases along the depth direction toward the substrate.
Shin addresses a known issue in vertically stacked nanosheet devices, teaching that the dopant concentration in the source/drain region often decreases toward the substrate. Shin recognizes that this concentration gradient results in higher electrical resistance in the lower source/drain region adjacent to the lower nanosheets (see e.g., Paras [0027], [0036], [0037], Figures 1 and 2A-2B).
It would have been obvious to one skilled in art to optimize the independently selectable ion concentrations taught by Lin so that consistent with Lin’s increasing channel junction extent toward the substrate the dopant concentration of the channel junction regions likewise increases toward the substrate. Shin provides an explicit motivation for this optimization by identifying the undesirable high resistance associated with the lower source/drain and lower nanosheet regions. Increasing the dopant concentration toward the lower channel junction regions would predictably reduce this resistance and improve current uniformity among the vertically stacked nanosheets.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize Lin’s independently selectable dopant concentrations such that the dopant concentration increases toward the substrate in view of Shin. Such optimization would have predictable reduced the resistance associated with the lower nanosheets regions and improved current uniformity among the vertically stacked channels.
Regarding claim 6, More, as modified by Zhang, Frougier, Lin and Shin, teaches the limitations of claim 5 as mentioned above. More does not explicitly teach
“wherein a first doped region in an uppermost layer of the second semiconductor material distal from the substrate has a first concentration of the first dopant, and a second doped region in a lowermost layer of the second semiconductor material closest to the substrate has a second concentration of the first dopant, wherein the second concentration is between about twice and about five times the first concentration”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Lin teaches doped channel junction regions 58A, 58B and 58C formed in the end portions of vertically stacked channel layers 54A, 54B and 54C. Figure 15B shows the lateral straggling of the doped channel junction regions increases toward the substrate such that the lower doped channel junction region extends farther into the channel than the vertically higher doped channel junction region.
Lin further teaches that the lateral straggling, ion concentration and dopant species of each doped channel junction region may be independently selected to obtain a desired junction characteristics and reduce channel resistance (see e.g., Paras [0059], [0108]).
While Lin teaches the lateral straggling of the doped channel junction regions increases toward the substrate, Lin does not explicitly teach the dopant concentration itself likewise increases along the depth direction toward the substrate.
Shin addresses a known issue in vertically stacked nanosheet devices, teaching that the dopant concentration in the source/drain region often decreases toward the substrate. Shin recognizes that this concentration gradient results in higher electrical resistance in the lower source/drain region adjacent to the lower nanosheets (see e.g., Paras [0027], [0036], [0037], Figures 1 and 2A-2B).
It would have been obvious to one skilled in art to optimize the independently selectable ion concentrations taught by Lin so that consistent with Lin’s increasing channel junction extent toward the substrate the dopant concentration of the channel junction regions likewise increases toward the substrate. Shin provides an explicit motivation for this optimization by identifying the undesirable high resistance associated with the lower source/drain and lower nanosheet regions. Furthermore, selecting the lowermost dopant concentration to be about twice and about five times the uppermost concentration represents a routine optimization of workable result effective variables to predictably minimize device resistance and improve electrical performance.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize Lin’s independently selectable dopant concentrations such that the lower most dopant concentration is about twice and about five times the uppermost dopant concentration in view of Shin. Such optimization would have predictable reduced the resistance associated with the lower nanosheets regions and improved current uniformity among the vertically stacked channels.
Regarding claim 7, More, as modified by Zhang, Frougier, Lin and Shin, teaches the limitations of claim 5 as mentioned above. More does not explicitly teach
“further comprising, after performing the ion implantation process, performing a thermal process to activate the first dopant”.
In a similar field of endeavor Zhang teaches
further comprising, after performing the ion implantation process, performing a thermal process to activate the first dopant (see e.g., after performing the ion implantation process a subsequent thermal process maybe performed to derive the implanted dopants into the channel regions, Para [0033], Figure 1).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Zhang’s teachings of further comprising, after performing the ion implantation process, performing a thermal process to activate the first dopant to activate and drive the implanted dopants farther into the channel regions.
Regarding claim 8, More, as modified by Zhang, Frougier, Lin and Shin, teaches the limitations of claim 5 as mentioned above. More further teaches
wherein forming the source/drain regions comprises:
selectively forming a first layer of source/drain material on the second end portions of the second semiconductor material and on an upper surface of the fin exposed by the source/drain openings; and (see e.g., first epitaxial layer 602 is etched back to form the epitaxial end caps 702 on end portions of semiconductor layers 122 and epitaxial base 704 in recesses 402, Para [0042], Figure 7)
after selectively forming the first layer of source/drain material, forming a second layer of source/drain material to fill the source/drain openings (see e.g., a second epitaxial layer 806 disposed on the epitaxial caps 702, the epitaxial base 704 and inner spacers and forms the bulk of source/drain regions of semiconductor device 200, Para [0044], Figure 8), wherein the source/drain regions are formed to have a second dopant, wherein a first concentration of the second dopant in the first layer of source/drain material is lower than a second concentration of the second dopant in the second layer of source/drain material (see e.g., the first epitaxial layer 602 and the second epitaxial layer 806 are both doped with either p-type or n-type dopants to support PMOS orNMOS configurations. The dopant concentration in second epitaxial layer 806 can be greater than the dopant concentration of first epitaxial layer 602, Paras [0037], [0038], [0045], Figures 8 and 10).
Regarding claim 9, More, as modified by Zhang, Frougier, Lin and Shin, teaches the limitations of claim 8 as mentioned above. More does not explicitly teach
“wherein a first doped region in an uppermost layer of the second semiconductor material distal from the substrate has a first concentration of the first dopant, wherein the first concentration of the first dopant is equal to or higher than the first concentration of the second dopant in the first layer of source/drain material”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Lin teaches doped channel junction regions 58A, 58B and 58C at the end portions of the nanosheet channels. Lin teaches that the dopant concentration of the doped channel junctions may be between about 1×10.sup.18 cm.sup.−3 and 1×10.sup.22 cm.sup.−3 (see e.g., Paras [0044], [0109]).
Lin further teaches the epitaxial source/drain regions 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. The first semiconductor material layer 92A may have a dopant concentration less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. The source/drain regions may have an impurity concentration of between about 1×10.sup.19 atoms/cm.sup.3 and about 1×10.sup.21 atoms/cm.sup.3 (see e.g., Paras [0089], [0091], Figures 18A-18B).
Accordingly, Lin teaches overlapping dopant concentration ranges for the doped channel junction regions and the source/drain region. Although Lin does not explicitly state that the dopant concentration of the uppermost channel junction is equal to or greater than the dopant concentration of first source/drain layer 92A, Lin explicitly teaches that channel junction ion concentration is independently selectable and that source/drain layers may also be provided with different dopant concentrations.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to select the dopant concentration of the uppermost channel junction region within Lin’s disclosed overlapping range such that it is equal to or greater than the dopant concentration of first source/drain layer 92A to obtain a desired source/drain to channel junction profile and reduce electrical resistance at the channel/source drain interface.
Regarding claim 10, More, as modified by Zhang, Frougier, Lin and Shin, teaches the limitations of claim 9 as mentioned above. More does not explicitly teach
“wherein the second dopant and the first dopant are of a same n-type or p-type”.
In a similar field of endeavor Lin teaches
wherein the second dopant and the first dopant are of a same n-type or p-type (see e.g., doped channel junction regions 58A, 58B and 58C may be implanted with n-type or p-type dopants to form n-type or p-type devices. Similarly, epitaxial source/drain regions maybe doped with the corresponding n-type or p-type impurities to complete respective device structures, Para [0042], [0089], Figures 18A-18D).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Lin’s teachings of wherein the second dopant and the first dopant are of a same n-type or p-type in the method of More to have the same n-type and p-type conductivity to match in accordance with the desired conductivity type of the transistor.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang), Frougier et al. (US 2023/0142410 A1; hereafter Frougier), Lin et al. (US 2022/0037465 A1; hereafter Lin) and Shin et al. (US 2020/0365586 A1; hereafter Shin) and further in view of Cheng et al. (US 2020/0266060 A1; hereafter Cheng).
Regarding claim 11, More, as modified by Zhang, Frougier, Lin and Shin, teaches the limitations of claim 10 as mentioned above. More does not explicitly teach
“wherein the second dopant in the source/drain regions diffuses into the doped regions of the second semiconductor material, wherein the diffused second dopant increases volumes of the doped regions”.
In a similar field of endeavor Cheng teaches
wherein the second dopant in the source/drain regions diffuses into the doped regions of the second semiconductor material, wherein the diffused second dopant increases volumes of the doped regions (see e.g., GAA nanosheet device having active channel layers 112, 114 and 116, source/drain contacts 140 and source/drain regions 150. A thermal anneal process is performed following the epitaxial growth and doping of the source/drain layers 150 to cause dopants to be injected into the source/drain extension contacts 140 and into portions of the active nanosheet channel layers 112, 114, and 116 that are in contact with the epitaxial semiconductor material of the source/drain extension contacts 140. This anneal process effectively results in extending the source/drain layer 150 into the semiconductor material of the end portions of the active nanosheet channel layers 112, 114, and 116, leading to a further decrease in parasitic resistance of the nanosheet FET device. Thus, the diffusion of source/drain dopant into channel ends increases the extent and therefore the volume of the doped channel end regions, Paras [0064], [0068], [0069], Figure 10).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Cheng’s teachings of wherein the second dopant in the source/drain regions diffuses into the doped regions of the second semiconductor material, wherein the diffused second dopant increases volumes of the doped regions in the method of More thereby reducing parasitic source/drain to channel resistance.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang), Frougier et al. (US 2023/0142410 A1; hereafter Frougier) and further in view of Lin et al. (US 2022/0037465 A1; hereafter Lin) and Cheng et al. (US 2020/0266060 A1; hereafter Cheng).
Regarding claim 15, More, as modified by Zhang and Frougier, teaches the limitations of claim 14 as mentioned above. More does not explicitly teach
“wherein the first dopant and the second dopant are of a same n-type or p-type,”.
In a similar field of endeavor Lin teaches
wherein the first dopant and the second dopant are of a same n-type or p-type (see e.g., doped channel junction regions 58A, 58B and 58C may be implanted with n-type or p-type dopants to form n-type or p-type devices. Similarly, epitaxial source/drain regions maybe doped with the corresponding n-type or p-type impurities to complete respective device structures, Para [0042], [0089], Figures 18A-18D).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Lin’s teachings of wherein the second dopant and the first dopant are of a same n-type or p-type in the method of More to have the same n-type and p-type conductivity to match in accordance with the desired conductivity type of the transistor.
More does not explicitly teach
“wherein the second dopant diffuses into the nanostructures, wherein the first dopant and the second dopant in the nanostructures are disposed in doped regions of the nanostructures”.
In a similar field of endeavor Cheng teaches
wherein the second dopant diffuses into the nanostructures (see e.g., GAA nanosheet device having active nanosheet channel layers 112, 114 and 116, epitaxial source/drain extension contacts 140 formed on exposed end portions of the channel layers and epitaxial source/drain layers 150 formed in contact with extension contacts 140. A thermal anneal process is performed following the epitaxial growth and doping of the source/drain layers 150 to cause dopants to be injected into the source/drain extension contacts 140 and into portions of the active nanosheet channel layers 112, 114, and 116 that are in contact with the epitaxial semiconductor material of the source/drain extension contacts 140. This anneal process effectively results in extending the source/drain layer 150 into the semiconductor material of the end portions of the active nanosheet channel layers 112, 114, and 116, leading to a further decrease in parasitic resistance of the nanosheet FET device, Para [0069], Figure 10), wherein the first dopant and the second dopant in the nanostructures are disposed in doped regions of the nanostructures (see e.g., the nanosheet channel layers 112, 114 and 116 end portions include the doped extension contacts 140 and dopants diffused from the source/drain regions, Figure 10).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Cheng’s teachings of wherein the second dopant diffuses into the nanostructures, wherein the first dopant and the second dopant in the nanostructures are disposed in doped regions of the nanostructures in the method of More to reduce source/drain to channel parasitic resistance.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang), Frougier et al. (US 2023/0142410 A1; hereafter Frougier), Lin et al. (US 2022/0037465 A1; hereafter Lin) and Cheng et al. (US 2020/0266060 A1; hereafter Cheng) and further in view of Shin et al. (US 2020/0365586 A1; hereafter Shin).
Regarding claim 16, More, as modified by Zhang, Frougier, Lin and Cheng, teaches the limitations of claim 15 as mentioned above. More does not explicitly teach
“wherein a total concentration of the first dopant and the second dopant in the doped regions of the nanostructures increases along a depth direction of the source/drain openings toward the substrate”.
In a similar field of endeavor Lin teaches doped channel junction regions 58A, 58B and 58C formed in the end portions of vertically stacked channel layers 54A, 54B and 54C. Figure 15B shows the lateral straggling of the doped channel junction regions increases toward the substrate such that the lower doped channel junction region extends farther into the channel than the vertically higher doped channel junction region.
Lin further teaches that the lateral straggling, ion concentration and dopant species of each doped channel junction region may be independently selected to obtain a desired junction characteristics and reduce channel resistance (see e.g., Paras [0059], [0108]).
While Lin teaches the lateral straggling of the doped channel junction regions increases toward the substrate, Lin does not explicitly teach the dopant concentration itself likewise increases along the depth direction toward the substrate.
Shin addresses a known issue in vertically stacked nanosheet devices, teaching that the dopant concentration in the source/drain region often decreases toward the substrate. Shin recognizes that this concentration gradient results in higher electrical resistance in the lower source/drain region adjacent to the lower nanosheets (see e.g., Paras [0027], [0036], [0037], Figures 1 and 2A-2B).
It would have been obvious to one skilled in art to optimize the independently selectable ion concentrations taught by Lin so that consistent with Lin’s increasing channel junction extent toward the substrate the dopant concentration of the channel junction regions likewise increases toward the substrate. Shin provides an explicit motivation for this optimization by identifying the undesirable high resistance associated with the lower source/drain and lower nanosheet regions. Furthermore, selecting the lowermost dopant concentration to be about twice and about five times the uppermost concentration represents a routine optimization of workable result effective variables to predictably minimize device resistance and improve electrical performance.
Cheng teaches doped source/drain layers 150 formed adjacent to the end portions of nanosheet channel layers 112, 114 and 116 and subsequently a thermal anneal that causes dopant from source/drain layers 150 to diffuse into the nanosheet end portions. Cheng explains that this drive-in effectively extends the source/drain region into the channel end portions and reduces parasitic resistance.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to apply Cheng’s source/drain dopant diffusion to Lin’s doped channel junction regions with he first dopant concentration increasing toward the substrate as suggested by Lin and Shin. The second dopant diffusing from the source/drain regions would be added to the first dopant already present in the doped channel end regions. Accordingly, the total concentration of first and second dopants in the doped regions would likewise increase along the depth direction of the source/drain openings toward the substrate thereby reducing resistance in the lower nanosheet regions and improving current uniformity among the vertically stacked channels.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang), Frougier et al. (US 2023/0142410 A1; hereafter Frougier), Lin et al. (US 2022/0037465 A1; hereafter Lin) and Cheng et al. (US 2020/0266060 A1; hereafter Cheng).
Regarding claim 21, More teaches a method of forming a semiconductor device (see e.g., Figures 1-11), the method comprising:
forming a fin structure that protrudes above a substrate (see e.g., fin structure 108 protruding from the substrate 106, Para [0022], Figure 2C), wherein the fin structure comprises layers of a first semiconductor material interleaved with layers of a second semiconductor material (see e.g., fin structure 108 includes a fin base 108A and fin top portion 108B with a stack of semiconductor layers including a first group of semiconductor layers 122 and a second group of semiconductor layers 124 stacked in an alternating configuration. Each semiconductor layer 122 and 124 can be epitaxially grown on its underlying layer and can include semiconductor materials different from each other. Each of the semiconductor layers 122 can be formed of silicon and each of semiconductor layers 124 can be formed of silicon germanium (SiGe), Paras [0022], ]0024], Figure 2C);
forming a dummy gate structure over the fin structure (see e.g., polysilicon gate structures 112 formed over the fin 108, Para [0027], Figures 3A-3b);
forming a source/drain opening in the fin structure at a first side of the dummy gate structure (see e.g., recesses 402 formed in the substrate 106 and between adjacent polysilicon gate structures 112, Para [0029], Figure 4),
replacing first end portions of the first semiconductor material exposed by the source/drain opening with inner spacers (see e.g., portions of semiconductor layers 124 can be etched back to form recessed regions and dielectric material can be deposited in the recessed regions to form inner spacers 127 for an NMOS device, Paras [0030], [0031], Figure 5);
….. forming a source/drain region in the source/drain opening (see e.g., source/drain regions including epitaxial end caps 702, epitaxial base 704 and second epitaxial layer 806 formed in the source/drain openings, Paras [0038], [0042], [0044], Figures 7-8);
forming a dielectric layer around the dummy gate structure; and (see e.g., interlayer dielectric (ILD) layer 1118 disposed on the source/drain regions and between spacers 114 of the polysilicon gate structures 112, Paras [0049], [0050], Figure 11)
replacing the dummy gate structure with a replacement gate structure (see e.g., the gate structure is replaced by metal gate structures including gate dielectric layers 1112, work function layers 1114 and gate electrodes 1116, Paras [0049], [0051], [0052], Figure 11).
More does not explicitly teach
“wherein the source/drain opening is formed to have a trapezoidal cross- section such that a width of the source/drain opening decreases along a depth direction of the source/drain opening;”
In a similar field of endeavor Frougier teaches
wherein the source/drain opening is formed to have a trapezoidal cross- section such that a width of the source/drain opening decreases along a depth direction of the source/drain opening (see e.g., source/drain recess is defined by sloped sidewalls such that the width of the opening decreases towards the substrate 105. The nano stack 102 is etched along the X-axis (i.e., cross section A) to taper the length of the nano stack 102. The taper of the nano stack 102 is such that each layer is progressively longer when going from the top layer to the bottom layer (e.g., the seventh layer 140 to the second layer 115). For example, the third layer 120 has a length L.sub.1, the fifth layer 130 has a length L.sub.2, and the seventh layer has a length L.sub.3. The nano stack 102 is tapered so that L.sub.1>L.sub.2>L.sub.3, Para [0052], Figures 12, 14 and 16);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Frougier’s teachings of wherein the source/drain opening is formed to have a trapezoidal cross- section such that a width of the source/drain opening decreases along a depth direction of the source/drain opening in the method of More to obtain a controlled source/drain recess profile suitable for subsequent inner spacer and source/drain formation.
More does not explicitly teach
“after the replacing, converting second end portions of the second semiconductor material exposed by the source/drain opening into doped regions by implanting a first dopant into the second end portions of the second semiconductor material, wherein a width of the doped regions increases along the depth direction of the source/drain opening;
after the converting, forming a source/drain region in the source/drain opening;”
In a similar field of endeavor Zhang teaches
after the replacing, converting second end portions of the second semiconductor material exposed by the source/drain opening into doped regions by implanting a first dopant into the second end portions of the second semiconductor material (see e.g., one or more implantation process may be performed whereby ions 133 are directed into the GAA stack 102, after formation of the S/D cavity 130 and inner spacer 134. The ions 133 may include p-type or n-type species depending on whether the GAA stack 102 is an nGAA stack or a pGAA stack. The ions are directed into the exposed surfaces of the GAA stack 102 that is, channels 106 at a non-zero angle (θ) relative to a plane (y-z plane) defined by an exterior surface of the GAA stack 102 within the S/D cavity 130, Para [0032], Figure 1),
after the converting, forming a source/drain region in the source/drain opening (see e.g., next, a S/D material 135 is epitaxially formed within the S/D cavities 130 to form S/D 136, Para [0034], Figure 2);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Zhang’s teachings of after the replacing, converting second end portions of the second semiconductor material exposed by the source/drain opening into doped regions by implanting a first dopant into the second end portions of the second semiconductor material, wherein a width of the doped regions increases along the depth direction of the source/drain opening; after the converting, forming a source/drain region in the source/drain opening in the method of More to provide controlled and more uniform doping of the exposed nanosheet channel regions.
More does not explicitly teach
“wherein a width of the doped regions increases along the depth direction of the source/drain opening;”
In a similar field of endeavor Lin teaches
wherein a width of the doped regions increases along the depth direction of the source/drain opening (see e.g., doped channel junction regions 58A, 58B and 58C formed in the end portions of vertically stacked channel layers 54A, 54B and 54C. Figure 15B shows the lateral straggling of the doped channel junction regions increases toward the substrate such that the lower doped channel junction region extends farther into the channel than the vertically higher doped channel junction region, Paras [0059], [0108], Figure 15B).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Lin’s teachings of wherein a width of the doped regions increases along the depth direction of the source/drain opening in the method of More to provide improved control of the source/drain to channel junction characteristics and reduce channel resistance.
Claims 22-24 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Zhang et al. (US 2025/0194127 A1; hereafter Zhang), Frougier et al. (US 2023/0142410 A1; hereafter Frougier), Lin et al. (US 2022/0037465 A1; hereafter Lin) and Cheng et al. (US 2020/0266060 A1; hereafter Cheng) and further in view of Shin et al. (US 2020/0365586 A1; hereafter Shin).
Regarding claim 22, More, as modified by Zhang, Frougier, Lin and Cheng, teaches the limitations of claim 21 as mentioned above. More does not explicitly teach
“wherein a concentration of the first dopant in the doped regions increases along the depth direction of the source/drain opening”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Lin teaches doped channel junction regions 58A, 58B and 58C formed in the end portions of vertically stacked channel layers 54A, 54B and 54C. Figure 15B shows the lateral straggling of the doped channel junction regions increases toward the substrate such that the lower doped channel junction region extends farther into the channel than the vertically higher doped channel junction region.
Lin further teaches that the lateral straggling, ion concentration and dopant species of each doped channel junction region may be independently selected to obtain a desired junction characteristics and reduce channel resistance (see e.g., Paras [0059], [0108]).
While Lin teaches the lateral straggling of the doped channel junction regions increases toward the substrate, Lin does not explicitly teach the dopant concentration itself likewise increases along the depth direction toward the substrate.
Shin addresses a known issue in vertically stacked nanosheet devices, teaching that the dopant concentration in the source/drain region often decreases toward the substrate. Shin recognizes that this concentration gradient results in higher electrical resistance in the lower source/drain region adjacent to the lower nanosheets (see e.g., Paras [0027], [0036], [0037], Figures 1 and 2A-2B).
It would have been obvious to one skilled in art to optimize the independently selectable ion concentrations taught by Lin so that consistent with Lin’s increasing channel junction extent toward the substrate the dopant concentration of the channel junction regions likewise increases toward the substrate. Shin provides an explicit motivation for this optimization by identifying the undesirable high resistance associated with the lower source/drain and lower nanosheet regions. Increasing the dopant concentration toward the lower channel junction regions would predictably reduce this resistance and improve current uniformity among the vertically stacked nanosheets.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to optimize Lin’s independently selectable dopant concentrations such that the dopant concentration increases toward the substrate in view of Shin. Such optimization would have predictable reduced the resistance associated with the lower nanosheets regions and improved current uniformity among the vertically stacked channels.
Regarding claim 23, More, as modified by Zhang, Frougier, Lin, Cheng and Shin, teaches the limitations of claim 22 as mentioned above. More further teaches
wherein forming the source/drain region comprises:
epitaxially growing a first layer of a source/drain material in the source/drain opening and on exterior surfaces of the doped regions of the second semiconductor material (see e.g., first epitaxial layer 602 is etched back to form the epitaxial end caps 702 on end portions of semiconductor layers 122 and epitaxial base 704 in recesses 402, Para [0042], Figure 7);
doping the first layer of the source/drain material with a second dopant (see e.g., the first epitaxial layer 602 may be doped with either p-type or n-type to support PMOS or NMOS configurations, Paras [0037], [0038], [0045], Figures 8 and 10),
epitaxially growing a second layer of the source/drain material in the source/drain opening and on the first layer of the source/drain material, wherein the second layer of the source/drain material fills the source/drain opening; and (see e.g., a second epitaxial layer 806 disposed on the epitaxial caps 702, the epitaxial base 704 and inner spacers and forms the bulk of source/drain regions of semiconductor device 200, Para [0044], Figure 8)
doping the second layer of the source/drain material with the second dopant, wherein the second layer of the source/drain material is doped with a higher concentration of the second dopant than the first layer of the source/drain material (see e.g., the second epitaxial layer 806 are both doped with either p-type or n-type dopants to support PMOS or NMOS configurations. The dopant concentration in second epitaxial layer 806 can be greater than the dopant concentration of first epitaxial layer 602, Paras [0037], [0038], [0045], Figures 8 and 10).
More does not explicitly teach
“wherein the first dopant and the second dopant are of a same n-type or p-type;”
In a similar field of endeavor Lin teaches
wherein the second dopant and the first dopant are of a same n-type or p-type (see e.g., doped channel junction regions 58A, 58B and 58C may be implanted with n-type or p-type dopants to form n-type or p-type devices. Similarly, epitaxial source/drain regions maybe doped with the corresponding n-type or p-type impurities to complete respective device structures, Para [0042], [0089], Figures 18A-18D).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Lin’s teachings of wherein the second dopant and the first dopant are of a same n-type or p-type in the method of More to have the same n-type and p-type conductivity to match in accordance with the desired conductivity type of the transistor.
Regarding claim 24, More, as modified by Zhang, Frougier, Lin, Cheng and Shin, teaches the limitations of claim 23 as mentioned above. More does not explicitly teach
“wherein forming the source/drain region further comprises performing a thermal anneal process after doping the second layer of the source/drain material with the second dopant,
wherein after performing the thermal anneal process, the second dopant diffuses into the doped regions and increases the width of the doped regions”.
In a similar field of endeavor Cheng teaches
wherein forming the source/drain region further comprises performing a thermal anneal process after doping the second layer of the source/drain material with the second dopant,
wherein after performing the thermal anneal process, the second dopant diffuses into the doped regions and increases the width of the doped regions (see e.g., a thermal anneal process is performed following the epitaxial growth and doping of the source/drain layers 150 to cause dopants to be injected into the source/drain extension contacts 140 and into portions of the active nanosheet channel layers 112, 114, and 116 that are in contact with the epitaxial semiconductor material of the source/drain extension contacts 140. This anneal process effectively results in extending the source/drain layer 150 into the semiconductor material of the end portions of the active nanosheet channel layers 112, 114, and 116, thereby increasing the lateral extent and thus the width of the doped regions, Para [0069], Figure 10).
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Cheng’s teachings of wherein forming the source/drain region further comprises performing a thermal anneal process after doping the second layer of the source/drain material with the second dopant, wherein after performing the thermal anneal process, the second dopant diffuses into the doped regions and increases the width of the doped regions in the method of More to reduce source/drain to channel parasitic resistance.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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