DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-10, 12, 13, 15, 16, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US 2019/0067444) (hereafter Ching).
Regarding claim 1, Ching discloses a semiconductor structure comprising:
a first fin (leftmost 104 in Fig. 16A, paragraph 0038) protruding from a first region (left portion of 102 in Fig. 16A) of a semiconductor substrate 102 (Fig. 16A, paragraph 0038);
a second fin (rightmost 104 in Fig. 16A, paragraph 0038) protruding from a second region (right portion of 102 in Fig. 16A) of the semiconductor substrate 102 (Fig. 16A), wherein the first region (left portion of 102 in Fig. 16A) of the semiconductor substrate is adjacent to the second region (right portion of 102 in Fig. 16A) of the semiconductor substrate;
an isolation region (112, 116, and 140 in Fig. 16A) disposed between the first fin (leftmost 104 in Fig. 16A) and the second fin (rightmost 104 in Fig. 16A);
a first portion (leftmost 148 and 150 in Fig. 16A) of a gate stack (148 and 150 in Fig. 16A, paragraph 0077) over and along sidewalls of the first fin (leftmost 104 in Fig. 16A);
a second portion (rightmost 148 and 150 in Fig. 16A) of the gate stack (148 and 150 in Fig. 16A) over and along sidewalls of the second fin (rightmost 104 in Fig. 16A); and
a conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) disposed between the first portion (leftmost 148 and 150 in Fig. 16A) of the gate stack (148 and 150 in Fig. 16A) and the second portion (rightmost 148 and 150 in Fig. 16A) of the gate stack, wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) extends into the isolation region (112, 116, and 140 in Fig. 16A), and wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) is electrically isolated from each of the first portion (leftmost 148 and 150 in Fig. 16A) of the gate stack (148 and 150 in Fig. 16A) and the second portion (rightmost 148 and 150 in Fig. 16A) of the gate stack by a dielectric layer 126 (Fig. 16A, paragraph 0053).
Regarding claim 5, Ching (utilized different elements for a first fin, a second fin, and a semiconductor substrate as applied in the Claim 1 in the above) discloses a semiconductor structure comprising:
a first fin (leftmost 106 in Fig. 16A, paragraph 0040) protruding from a first region (leftmost 104 in Fig. 16A) of a semiconductor substrate (102 and 104 in Fig. 16A, paragraph 0038);
a second fin (rightmost 106 in Fig. 16A, paragraph 0040) protruding from a second region (rightmost 104 in Fig. 16A) of the semiconductor substrate 102 (Fig. 16A), wherein the first region (leftmost 104 in Fig. 16A) of the semiconductor substrate (102 and 104 in Fig. 16A) is adjacent to the second region (rightmost 106 in Fig. 16A) of the semiconductor substrate;
an isolation region (112, 116, and 140 in Fig. 16A) disposed between the first fin (leftmost 106 in Fig. 16A) and the second fin (rightmost 106 in Fig. 16A);
a first portion (leftmost 148 and 150 in Fig. 16A) of a gate stack (148 and 150 in Fig. 16A, paragraph 0077) over and along sidewalls of the first fin (leftmost 106 in Fig. 16A);
a second portion (rightmost 148 and 150 in Fig. 16A) of the gate stack (148 and 150 in Fig. 16A) over and along sidewalls of the second fin (rightmost 106 in Fig. 16A);
a conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) disposed between the first portion (leftmost 148 and 150 in Fig. 16A) of the gate stack (148 and 150 in Fig. 16A) and the second portion (rightmost 148 and 150 in Fig. 16A) of the gate stack, wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) extends into the isolation region (112, 116, and 140 in Fig. 16A), and wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) is electrically isolated from each of the first portion (leftmost 148 and 150 in Fig. 16A) of the gate stack (148 and 150 in Fig. 16A) and the second portion (rightmost 148 and 150 in Fig. 16A) of the gate stack by a dielectric layer 126 (Fig. 16A, paragraph 0053); and
wherein the first region (leftmost 104 in Fig. 16A) of the semiconductor substrate (102 and 104 in Fig. 16A) is oppositely doped (see paragraph 0058, wherein “p-type FinFET devices”; see paragraph 0065, wherein “n-type FinFET devices”; and see paragraph 0038, wherein “the fin structures 104 doped with n-type dopants are used in n-type FinFETs (e.g., NMOS devices), while the fin structures 104 with upper sections 106 doped with p-type dopants are used in in p-type FinFETs (e.g., PMOS devices)”) from the second region (rightmost 104 in Fig. 16A) of the semiconductor substrate.
Regarding claim 6, Ching further discloses the semiconductor structure of claim 5, wherein a first portion (left 152 between second 148 and third 148 from the left corner of Fig. 16A) of the conductive contact overlaps the first region (leftmost 104 in Fig. 16A) of the semiconductor substrate (102 and 104 in Fig. 16A), and a second portion (right 152 between second 148 and third 148 from the left corner of Fig. 16A) of the conductive contact overlaps the second region (rightmost 104 in Fig. 16A) of the semiconductor substrate (102 and 104 in Fig. 16A).
Regarding claim 7, Ching further discloses the semiconductor structure of claim 1, wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A, paragraph 0083, wherein “cobalt (Co), tungsten (W), copper (Cu), nickel (Ni), ruthenium (Ru), or other suitable materials”) comprises tungsten, cobalt, copper, a combination thereof.
Regarding claim 8, Ching discloses a semiconductor structure comprising:
a substrate (102 and 104 in Fig. 16A, paragraph 0038) having a first region (leftmost 104 in Fig. 16A) and a second region (rightmost 104 in Fig. 16A), wherein the first region (leftmost 104 in Fig. 16A) of the substrate is oppositely doped (see paragraph 0058, wherein “p-type FinFET devices”; see paragraph 0065, wherein “n-type FinFET devices”; and see paragraph 0038, wherein “the fin structures 104 doped with n-type dopants are used in n-type FinFETs (e.g., NMOS devices), while the fin structures 104 with upper sections 106 doped with p-type dopants are used in in p-type FinFETs (e.g., PMOS devices)”) from the second region (rightmost 104 in Fig. 16A) of the substrate;
a first semiconductor strip (leftmost 106 in Fig. 16A, paragraph 0040) extending from the first region (leftmost 104 in Fig. 16A) of the substrate (102 and 104 in Fig. 16A);
a second semiconductor strip (rightmost 106 in Fig. 16A, paragraph 0040) extending from the second region (rightmost 104 in Fig. 16A) of the substrate;
an isolation region 138 (Fig. 16A, paragraph 0068) disposed between (see top view of Fig. 16A, wherein a portion of 138 is between leftmost 106 and rightmost 106) the first semiconductor strip (leftmost 106 in Fig. 16A) and the second semiconductor strip (rightmost 106 in Fig. 16A);
a gate stack (148 and 150 in Fig. 16A, paragraph 0077) over and along sidewalls of the first semiconductor strip (leftmost 106 in Fig. 16A) and the second semiconductor strip (rightmost 106 in Fig. 16A); and
a contact (152 between second 148 and third 148 from the left corner of Fig. 16A) extending through the gate stack (148 and 150 in Fig. 16A) and the isolation region (112, 116, and 140 in Fig. 16A), wherein the contact 152 (Fig. 16B) extends below a bottommost surface of the isolation region 138 (Fig. 16B).
Regarding claim 9, Ching further discloses the semiconductor structure of claim 8, further comprising a dielectric liner (126 and 140 in Fig. 16A) on a bottom surface and sidewalls of the contact (152 between second 148 and third 148 from the left corner of Fig. 16A).
Regarding claim 10, Ching further discloses the semiconductor structure of claim 9, wherein the dielectric liner (126 and 140 in Fig. 16A) electrically isolates the gate stack (148 and 150 in Fig. 16A) from the contact (152 between second 148 and third 148 from the left corner of Fig. 16A).
Regarding claim 12, Ching further discloses the semiconductor structure of claim 8, wherein the contact (152 between second 148 and third 148 from the left corner of Fig. 16A) extends along a lengthwise direction that is parallel to a lengthwise direction of the first semiconductor strip (leftmost 106 in Fig. 16A) and the second semiconductor strip (rightmost 106 in Fig. 16A).
Regarding claim 13, Ching further discloses the semiconductor structure of claim 12, wherein the contact (152 between second 148 and third 148 from the left corner of Fig. 16A, paragraph 0083, wherein “cobalt (Co), tungsten (W), copper (Cu), nickel (Ni), ruthenium (Ru), or other suitable materials”) comprises tungsten, cobalt, copper, or a combination thereof.
Regarding claim 15, Ching discloses a semiconductor structure comprising:
a first fin (leftmost 104 in Fig. 16A, paragraph 0038) protruding from a first region (left portion of 102 in Fig. 16A) of a semiconductor substrate 102 (Fig. 16A, paragraph 0038);
a second fin (rightmost 104 in Fig. 16A, paragraph 0038) protruding from a second region (right portion of 102 in Fig. 16A) of the semiconductor substrate 102 (Fig. 16A), wherein the first region (left portion of 102 in Fig. 16A) of the semiconductor substrate 102 (Fig. 16A) is adjacent to the second region (right portion of 102 in Fig. 16A) of the semiconductor substrate;
an insulating layer (112, 116, and 140 in Fig. 16A) disposed between the first fin (leftmost 104 in Fig. 16A) and the second fin (rightmost 104 in Fig. 16A);
a first gate stack (first 148 and fourth 148 from the left corner of Fig. 16A, paragraph 0077) disposed over and along sidewalls of the first fin (leftmost 104 in Fig. 16A), and over and along sidewalls of the second fin (rightmost 104 in Fig. 16A);
a second gate stack (second 148 and third 148 from the left corner of Fig. 16A, paragraph 0077) disposed over and along sidewalls of the first fin (leftmost 104 in Fig. 16A), and over and along sidewalls of the second fin (rightmost 104 in Fig. 16A); and
a conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) disposed between a first portion (first 148 from the left corner of Fig. 16A) of the first gate stack (first 148 and fourth 148 from the left corner of Fig. 16A) and a second portion (fourth 148 from the left corner of Fig. 16A) of the first gate stack, wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) is also disposed between a first portion (second 148 from the left corner of Fig. 16A) of the second gate stack (second 148 and third 148 from the left corner of Fig. 16A) and a second portion (third 148 from the left corner of Fig. 16A) of the second gate stack.
Regarding claim 16, Ching further discloses the semiconductor structure of claim 15, wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) is electrically isolated from each of the first portion (first 148 from the left corner of Fig. 16A) of the first gate stack (first 148 and fourth 148 from the left corner of Fig. 16A), the second portion (fourth 148 from the left corner of Fig. 16A) of the first gate stack, the first portion (second 148 from the left corner of Fig. 16A) of the second gate stack (second 148 and third 148 from the left corner of Fig. 16A), and the second portion third 148 from the left corner of Fig. 16A) of the second gate stack by a dielectric layer 126 (Fig. 16A, paragraph 0053).
Regarding claim 18, Ching further discloses the semiconductor structure of claim 15, wherein a bottom surface of the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) is higher than a bottommost surface of the insulating layer (112, 116, and 140 in Fig. 16A).
Regarding claim 19, Ching (utilized different elements for an insulating layer as applied in the Claim 15 in the above) discloses a semiconductor structure comprising:
a first fin (leftmost 104 in Fig. 16A, paragraph 0038) protruding from a first region (left portion of 102 in Fig. 16A) of a semiconductor substrate 102 (Fig. 16A, paragraph 0038);
a second fin (rightmost 104 in Fig. 16A, paragraph 0038) protruding from a second region (right portion of 102 in Fig. 16A) of the semiconductor substrate 102 (Fig. 16A), wherein the first region (left portion of 102 in Fig. 16A) of the semiconductor substrate 102 (Fig. 16A) is adjacent to the second region (right portion of 102 in Fig. 16A) of the semiconductor substrate;
an insulating layer 138 (Fig. 16A, paragraph 0068) disposed between (see top view of Fig. 16A, wherein a portion of 138 is between leftmost 104 and rightmost 104) the first fin (leftmost 104 in Fig. 16A) and the second fin (rightmost 104 in Fig. 16A);
a first gate stack (first 148 and fourth 148 from the left corner of Fig. 16A, paragraph 0077) disposed over and along sidewalls of the first fin (leftmost 104 in Fig. 16A), and over and along sidewalls of the second fin (rightmost 104 in Fig. 16A);
a second gate stack (second 148 and third 148 from the left corner of Fig. 16A, paragraph 0077) disposed over and along sidewalls of the first fin (leftmost 104 in Fig. 16A), and over and along sidewalls of the second fin (rightmost 104 in Fig. 16A);
a conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) disposed between a first portion (first 148 from the left corner of Fig. 16A) of the first gate stack (first 148 and fourth 148 from the left corner of Fig. 16A) and a second portion (fourth 148 from the left corner of Fig. 16A) of the first gate stack, wherein the conductive contact (152 between second 148 and third 148 from the left corner of Fig. 16A) is also disposed between a first portion (second 148 from the left corner of Fig. 16A) of the second gate stack (second 148 and third 148 from the left corner of Fig. 16A) and a second portion (third 148 from the left corner of Fig. 16A) of the second gate stack; and
wherein a bottom surface of the conductive contact 152 (Fig. 16B) is lower than a bottommost surface of the insulating layer 138 (Fig. 16B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 2019/0067444) (hereafter Ching).
Regarding claim 2, Ching discloses the semiconductor structure of claim 1, however Ching does not explicitly disclose a thickness of the dielectric layer is in a range from 1 nm to 5 nm.
Regarding the limitation, “a thickness of the dielectric layer is in a range from 1 nm to 5 nm”, Ching discloses a thickness of the dielectric layer 126 (Fig. 16A, paragraph 0053) is between about 6 nm and about 8 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form a thickness of the dielectric layer is in a range from 1 nm to 5 nm, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, since a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 11, Ching discloses the semiconductor structure of claim 9, however Ching does not explicitly disclose the dielectric liner has a thickness that is in a range from 1 nm to 5 nm.
Regarding the limitation, “the dielectric liner has a thickness that is in a range from 1 nm to 5 nm”, Ching discloses a thickness of the dielectric layer 126 (Fig. 16A, paragraph 0053) is between about 6 nm and about 8 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the dielectric liner has a thickness that is in a range from 1 nm to 5 nm, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, since a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 17, Ching discloses the semiconductor structure of claim 16, however Ching does not explicitly disclose the dielectric layer has a thickness that is in a range from 1 nm to 5 nm.
Regarding the limitation, “the dielectric layer has a thickness that is in a range from 1 nm to 5 nm”, Ching discloses a thickness of the dielectric layer 126 (Fig. 16A, paragraph 0053) is between about 6 nm and about 8 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the dielectric layer has a thickness that is in a range from 1 nm to 5 nm, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, since a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ching as applied to claim 1 above, and further in view of Ho et al. (US 2017/0213901) (hereafter Ho).
Regarding claim 3, Ching discloses the semiconductor structure of claim 1, however Ching does not disclose the dielectric layer comprises silicon oxide, silicon nitride, or silicon oxynitride.
Ho discloses the dielectric layer (element number is not shown in Fig. 23A but see 328 in Fig. 18A, paragraph 0043, wherein “the dielectric layer includes one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or other suitable material”) comprises silicon oxide, silicon nitride, or silicon oxynitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the dielectric layer comprises silicon oxide, silicon nitride, or silicon oxynitride, as taught by Ho, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claims 4, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ching as applied to claims 1, 12, and 15 above, and further in view of Zhu et al. (US 2018/0033699) (hereafter Zhu).
Regarding claim 4, Ching discloses the semiconductor structure of claim 1, however Ching does not disclose the conductive contact extends into the semiconductor substrate.
Zhu discloses the conductive contact 1048 (Fig. 21, paragraph 0064) extends into the semiconductor substrate (1002, 1002-1, and F in Fig. 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the conductive contact extends into the semiconductor substrate, as taught by Zhu, since the source/drain contact/conductive contact provides an electrical connection between the source/drain to other devices.
Regarding claim 14, Ching discloses the semiconductor structure of claim 12, however Ching does not disclose the contact extends into the first region of the substrate and the second region of the substrate.
Zhu discloses the contact 1048 (Fig. 21, paragraph 0064) extends into the first region (left portion of 1002, 1002-1 and F in Fig. 21) of the substrate (1002, 1002-1, and F in Fig. 21) and the second region (right portion of 1002, 1002-1 and F in Fig. 21) of the substrate (1002, 1002-1, and F in Fig. 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the contact extends into the first region of the substrate and the second region of the substrate, as taught by Zhu, since the source/drain contact/conductive contact provides an electrical connection between the source/drain to other devices.
Regarding claim 20, Ching discloses the semiconductor structure of claim 15, however Ching does not disclose the conductive contact extends into the first region of the semiconductor substrate and the second region of the semiconductor substrate.
Zhu discloses the conductive contact 1048 (Fig. 21, paragraph 0064) extends into the first region (left portion of 1002, 1002-1 and F in Fig. 21) of the semiconductor substrate (1002, 1002-1, and F in Fig. 21) and the second region (right portion of 1002, 1002-1 and F in Fig. 21) of the semiconductor substrate (1002, 1002-1, and F in Fig. 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the conductive contact extends into the first region of the semiconductor substrate and the second region of the semiconductor substrate, as taught by Zhu, since the source/drain contact/conductive contact provides an electrical connection between the source/drain to other devices.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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