Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 3, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1 and 4 are rejected under 35 U.S.C. 101 as claiming exactly the same invention as that of claim 11 and claim 12 of prior Patent No. US 12,063,792 B2., respectively.
Regarding Claim 1, Patent No.: US 12,063,792 B2. discloses a semiconductor device, comprising: a magnetic tunneling junction (MTJ) and a hard mask on a substrate (Claim 11); a first inter-metal dielectric (IMD) layer around the MTJ (Claim 11); a first metal interconnection adjacent to the MTJ (Claim 11); a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection (Claim 11); and a stop layer around the channel layer (Claim 11).
Regarding Claim 4, Patent No.: US 12,063,792 B2, as applied to claim 1, discloses the semiconductor device, wherein top surfaces of the channel layer and the stop layer are coplanar (Claim 12).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based e-Terminal Disclaimer may be filled out completely online using web-screens. An e-Terminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about e-Terminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-3 and 5-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-14 of U.S. Patent No. US 12,063,792 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding Claim 2, Patent No.: US 12,063,792 B2, as applied to claim 1, discloses the semiconductor device, further comprising a second metal interconnection under the MTJ, wherein bottom surfaces of the first metal interconnection and the second metal interconnection are coplanar (Claim 9 together with Claim 11).
Regarding Claim 3, Patent No.: US 12,063,792 B2, as applied to claim 2, discloses the semiconductor device, wherein the MTJ comprises: a pinned layer on the second metal interconnection (Claim 10 together with Claim 11); a second barrier layer on the pinned layer (Claim 10 together with Claim 11); and a free layer on the second barrier layer (Claim 10 together with Claim 11).
Regarding Claim 5, Patent No.: US 12,063,792 B2, as applied to claim 1, discloses the semiconductor device, wherein the channel layer and the first metal interconnection comprise different materials (Claim 13 together with Claim 11).
Regarding Claim 6, Patent No.: US 12,063,792 B2, as applied to claim 1, discloses the semiconductor device, wherein the channel layer comprises metal (Claim 14 together with Claim 11).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Song et al.; Pub. No. US 2021/0134339 A1 – This prior art teaches a SOT-MRAM with some similarities to the claimed invention of the instant application.
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06/26/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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