Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/03/2024 , and 02/09/2026 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 12,14-17 rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-3,5 of U.S. Patent No. US 11,784,172 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claims in US 11,784,172 B2 teaches the scope of the claim limitations of application 18/762,172 being examined.
Attached below is a table of the claim(s) rejected under double patenting by the claim(s) of the parent case.
Claim numbering that are anticipated
Instant Application Claims
Conflicting Application/Patent Claims by Yu et al, (US 11,784,172 B2)
1
12. A method comprising: forming a wafer comprising: a plurality of low-k dielectric layers; a non-low-k dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers; and a first plurality of bond pads in the non-low-k dielectric layer; bonding a capacitor die to the wafer, wherein the capacitor die comprises: a second plurality of bond pads, wherein the second plurality of bond pads are physically joined to the first plurality of bond pads; and a capacitor electrically coupled to the second plurality of bond pads; encapsulating the capacitor die in a gap-fill layer; after the capacitor die is encapsulated, forming an aluminum-containing pad over the capacitor die, wherein the aluminum-containing pad is electrically coupled to the wafer; and forming a polymer layer over the aluminum-containing pad.
1. A method comprising: bonding a capacitor die to a device die, wherein the device die comprises: a first semiconductor substrate; active devices at a surface of the first semiconductor substrate; a plurality of low-k dielectric layers; a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers; and a first plurality of bond pads in the first dielectric layer; wherein the capacitor die is free from active devices therein, and wherein the capacitor die comprises: a second dielectric layer bonding to the first dielectric layer; a second plurality of bond pads in the second dielectric layer, wherein the second plurality of bond pads are bonded to the first plurality of bond pads; and a capacitor electrically coupled to the second plurality of bond pads; after the capacitor die is bonded to the device die, forming an aluminum-containing pad over the capacitor die, wherein the aluminum-containing pad is electrically coupled to the device die; and forming a polymer layer over the aluminum-containing pad.
5. The method of claim 1 further comprising, before the aluminum-containing pad is formed: forming gap-filling regions to encapsulate the capacitor die; and planarizing the gap-filling regions and the capacitor die.
2
15. The method of claim 12, wherein the wafer is free from polymer layers therein.
2. The method of claim 1, wherein each of the device die and the capacitor die is free from polymer layers therein.
3
16. The method of claim 13, wherein the capacitor die is further free from polymer layers therein
2. The method of claim 1, wherein each of the device die and the capacitor die is free from polymer layers therein
4
17. The method of claim 12, wherein each of the wafer and the capacitor die is free from aluminum-containing pads therein.
3. The method of claim 1, wherein each of the device die and the capacitor die is free from aluminum-containing pads therein.
.
Allowable Subject Matter
Claims 1-11,18-20 allowed.
Claims 13-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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