DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 1-16 and amended claim 17, canceled claim 20, newly added claim 21 in the reply filed on 01/05/2025 is acknowledged.
Claims 1-19, 21 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/03/2024 is filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-19, 21 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,068,300. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of U.S. Patent No. 12,068,300 disclose all limitations cited in claims 1-19, 21 of present application.
Regarding claim 1, Claim 1 of U.S. Patent No. 12,068,300 discloses:
A CoWoS comprising:
A chi-on-wafer (CoW) sub-assembly comprising a plurality of IC dies mounted on a front side of an interposer (lines 58-60, Col. 13), and
A package substrate having a front side comprising a top metallization stack and a backside opposite the front side comprising a bottom metallization stack (lines 62-67),
Wherein a total metal thickness of the top metallization stack of the package substrate is greater than a total metal thickness of the bottom metallization stack of the package substrate (lines 8-11).
Regarding claim 2, Claim 2 of U.S. Patent No. 12,068,300 discloses:
wherein T(top) is the total metal thickness of the top metallization stack of the package substrate and T(bottom) is the total metal thickness of the bottom metallization stack of the package substrate (lines 12-22, Col. 14).
Regarding claim 3, Claim 3 of U.S. Patent No. 12,068,300 discloses:
Where T(top) is the total metal thickness of the top metallization stack of the package substrate and T(bottom) is the total metal thickness of the bottom metallization stack of the package substrate (lines 24-34, Col. 14).
Regarding claim 4, Claim 4 of U.S. Patent No. 12,068,300 discloses:
Where T (top) is the total metal thickness of the top metallization stack of the package substrate and T (bottom) is the total metal chicness of the bottom metallization stack of the package substrate (lines 35-45, Col. 14).
Regarding claim 5, Claim 5 of U.S. Patent No. 12,068,300 discloses:
Further comprising an underfill material comprising an electrically nonconductive molding compound disposed between the backside of the interposer and the front side of the package substrate (lines 46-50, Col. 14).
Regarding claim 6, Claim 6 of U.S. Patent No. 12,068,300 discloses:
Wherein the package substrate includes a planar core disposed between the top metallization stack and the bottom metallization stack, the planar core disposed between the top metallization stack and the bottom metallization stack, the planar core having an in-plane coefficient of thermal expansion of 15 ppm/0c or less over a temperature range of 30-129 oC.(lines 51-56, Col. 14).
Regarding claim 7, Claim 7 of U.S. Patent No. 12,068,300 discloses:
Wherein the CoWoS semiconductor assembly is a CoWoS semiconductor assembly is a CoWoS semiconductor package produced by singulation of a CoWoS semiconductor wafer (lines 53-60, Col. 14).
Regarding claim 8, Claim 8 of U.S. Patent No. 12,068,300 discloses:
Wherein the CoWoS semiconductor assembly is a CoWoS semiconductor wafer and the package substrate is configured by the top metallization stack and the bottom metallization stack to warp in a same direction as the CoW subassembly when the CoWoS semiconductor wafer is heated from 30-150 oC (lines 61-67, Col. 14).
Regarding claim 9, Claim 9 of U.S. Patent No. 12,068,300 discloses:
wherein the package substrate includes a planar core disposed between the top metallization stack and the bottom metallization stack, the planar core having an in-plane coefficient of thermal expansion of 15 ppm/oC or less over a temperature range of 30-120 oC the CoWoS further includes an underfill material and T (top) is total metal thickness of the top metallization stack of the package substrate and T (bottom) is the total metal thickness of the bottom metallization stack of the package substrate (lines 1-20, Col. 15).
Regarding claim 10, Claim 10 of U.S. Patent No. 12,068,300 discloses:
Where T (core) is the thickness of the planar core (lines 22-29, Col. 15).
Regarding claim 11, Claim 11 of U.S. Patent No. 12,068,300 discloses:
A siliconinterposer, IC dies mount on a front side of the silicon interposer and a substrate having a front side comprising a top metallization stack and a backside opposite the front side comprising a bottom metallization stack, a backside of the silicon interposer being secured to the front side of the substrate, wherein the substrate is configured to warp in a same direction as the silicon interposer whn the semicodncutor assembly is at 150 oC (lines 30-47, Col. 15).
Regarding claim 12, Claim 12 of U.S. Patent No. 12,068,300 discloses:
Wherein the substrate is configured to warp in the same direction as the siicon interposer when the assembly is at 150 oC by a total metal thickness of the top metallization stack being greater than a total metal thickness of the bottom metallization stack (lines 47-52, Col. 15).
Regarding claim 13, Claim 13 of U.S. Patent No. 12,068,300 discloses:
Where T (top) is the total metal thickness of the top metallization stack and T (bottom) is the total metal thickness of the bottom metallization stack (lines 53-62, Col. 15).
Regarding claim 14, Claim 14 of U.S. Patent No. 12,068,300 discloses:
The assembly of claim 11, further comprising an underfill material comprising an electrically nonconductive molding compound disposed between the backside of the interposer and the front side of the substrate (lines 1-5, Col. 16).
Regarding claim 15, Claim 15 of U.S. Patent No. 12,068,300 discloses:
The assembly of claim 11, wherein the package substrate includes a planar core disposed between the top metallization stack and the bottom metallization stack, the planar core having an in-planar core having an in-plane CTE of 15 ppm/0C or less over a T range of 30-120 oC (lines 5-30, Col. 16).
Regarding claim 16, Claim 10 of U.S. Patent No. 12,068,300 discloses:
The assembly of claim 11, wherein T (core) is the thickness of the planar core (lines 22-29, Col. 15).
Regarding claim 17, Claim 1, 9, 15, 16, of U.S. Patent No. 12,068,300 discloses:
A package comprising:
A package substrate having a front side comprising a top metallization stack and a backside opposite the front side comprising a bottom metallization stack and a planar core disposed between the top metallization stack and the bottom metallization stack, the planar core having an in-plane coefficient of CTE of 15 ppm/oC or less over a temperature range of 30-120 oC (Claim 9: (lines 1-20, Col. 15),
The planar core having through-vias passing through the planar core providing electrical connection between the top metallization stack and the bottom metallization stack,
An interposer disposed on the top metallization stack, the interposer having bias passing through the interposer, and IC dies disposed on the interposer and electrically connected with the top metallization stack of the package substrate by the vias passing through the interposer, wherein a total metal thickness of the top metallization stack of the package substrate is greater than a total metal thickness of the bottom metallization stack of the package substrate (Claim 1, lines 58-67, Col. 13; lines 1-11, Col. 14).
Regarding claim 18, Claim 13 of U.S. Patent No. 12,068,300 discloses:
Where T (top) is the total metal thickness of the top metallization stack and T (bottom) is the total metal thickness of the bottom metallization stack (lines 53-62, Col. 15).
Regarding claim 19, Claim 4 of U.S. Patent No. 12,068,300 discloses:
Where T (top) is the total metal thickness of the top metallization stack of the package substrate and T (bottom) is the total metal chicness of the bottom metallization stack of the package substrate (lines 35-45, Col. 14).
Regarding claim 21, Claim 10 of U.S. Patent No. 12,068,300 discloses:
Where T (core) is the thickness of the planar core (lines 22-29, Col. 15).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818