YNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (Pub. No.: US 2018/0122822) (hereinafter LEE) in view of YOON and further in view of KANAMORI (Pub. No.: US 2017/0221921).
Re claim 1, LEE, FIG. 1 teaches a method for preparing a vertical memory structure, comprising:
providing a substrate (100);
forming an impurity layer (107, ¶ [0039]) at an upper portion of the substrate;
forming a semiconductor stack including a lower semiconductor pattern structure (251, [0021]) filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate;
forming a plurality of gate electrodes (343/345/347, [0017]) surrounding a sidewall of the semiconductor stack, wherein the plurality of gate electrodes are at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction;
forming a contact plug (270/380/390, [0040]) over the semiconductor stack, wherein the contact plug comprises a lower portion (270), a middle portion (380) and an upper portion (390), and a width of the middle portion (horizontal width 380) is less than a width of the lower portion (horizontal width 270); and
forming a bit line (390, [0041]) over the contact plug.
LEE fails to teach forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.
KANAMORI teaches forming a plurality of air gap structures (235, FIG. 3, [0067]) disposed at outer sides of the plurality of gate electrodes (363/365/367) respectively;
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing the coupling that may occur between neighboring by implementing the air gap as taught by KANAMORI, [0005].
Re claim 2, in the combination, KANAMORI, FIG. 1 teaches a method for preparing the vertical memory structure of claim 1, wherein forming the plurality of air gap structures comprises:
forming a plurality of energy removable blocks (210, FIG. 16, [0098]) disposed at the outer sides of the plurality of gate electrodes respectively; and
performing a heat treatment process to transform the plurality of energy removable blocks to the plurality of air gap structures (220), respectively, wherein each of the air gap structures comprises a liner layer (232, [0066]) and an air gap (235), and the liner layer encloses the air gap (235).
Re claim 3, in the combination, LEE, FIG. 1 teaches the method for preparing the vertical memory structure of claim 1, wherein forming the semiconductor stack comprises:
forming the lower semiconductor pattern structure (251) in the recess; and
forming an upper semiconductor pattern structure (260/250/240) above the lower semiconductor pattern (251) in the recess, wherein the upper semiconductor pattern is in contact with the lower portion of the contact plug (270/380/390).
Re claim 4, KANAMORI, FIG. 1 teaches the method for preparing the vertical memory structure of claim 3, wherein forming the lower semiconductor pattern structure in the recess comprises:
forming a first undoped semiconductor pattern (160, [0023]);
forming a first diffusion prevention (170) pattern over the first undoped semiconductor pattern;
forming a doped semiconductor pattern (180) over the first diffusion prevention pattern;
forming a second diffusion prevention pattern (190) over the doped semiconductor pattern; and
forming a second undoped semiconductor pattern (200) over the second diffusion prevention pattern.
Re claim 5, in the combination, LEE, FIG. 1 teaches the method for preparing the vertical memory structure of claim 4, wherein the first diffusion prevention pattern (170) and the second diffusion prevention pattern (190) comprise carbon [0023].
Re claim 6, in the combination, LEE, FIG. 1 teaches the method for preparing the vertical memory structure of claim 4, wherein the second diffusion prevention pattern further comprises boron [0023].
Re claim 7, in the combination, LEE, FIG. 1 teaches the method for preparing the vertical memory structure of claim 3, wherein forming the upper semiconductor pattern structure comprises:
forming a charge storage structure (240, [0031]);
forming an upper channel structure (250);
forming a filling pattern (260, [0030]), wherein the upper channel structure and the filling pattern are penetrating through the charge storage structure into the lower semiconductor pattern structure; and
forming a capping pattern (270, [0032]) over the charge storage structure, the upper channel structure and the filling pattern, wherein the capping pattern is in contact with the lower portion of the contact plug (380/390), and a width the capping pattern is greater than the width of the lower portion (380).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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