Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated July 3, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed July 3, 2024 have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 8-15, 17, 19 and 20 of U.S. Patent No. 12057153 [‘153]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘153
1. A probabilistic random number generator, comprising: a memory cell comprising a magnetic tunnel junction (MTJ); and a current source coupled to the MTJ, wherein the current source comprises: a plurality of current paths disposed in parallel with one another; and a plurality of MTJs on the plurality of current paths, respectively.
1. A probabilistic random number generator, comprising: a memory cell comprising a magnetic tunnel junction (MTJ); and a current source coupled to the MTJ, the current source configured to provide a current pulse shape to the MTJ to generate a probabilistic random bit, where the current pulse shape induces a switching probability for the MTJ that ranges between 5% and 95%; wherein the current source comprises: a plurality of current paths; and a plurality of MTJs on the plurality of current paths, respectively.
2. The probabilistic random number generator of claim 1, further comprising: a plurality of transistors arranged on the plurality of current paths, respectively, wherein each current path includes a respective transistor and a respective MTJ arranged in series on that current path.
10. The probabilistic random number generator of claim 1, wherein the plurality of current paths are disposed in parallel with one another; and the current source further comprising: a plurality of transistors arranged on the plurality of current paths, respectively, wherein each current path includes a respective transistor and a respective MTJ arranged in series on that current path.
3. The probabilistic random number generator of claim 1, further comprising:
a controller configured to write a multi-bit digital code to the plurality of MTJs, wherein a value of the multi-bit digital code selects a predetermined current pulse shape from a plurality of predetermined current pulse shapes to be applied to the plurality of MTJs to induce generation of a probabilistic random bit.
11. The probabilistic random number generator of claim 10, further comprising: a controller configured to write a multi-bit digital code to the plurality of MTJs, wherein a value of the multi-bit digital code selects a predetermined current pulse shape from a plurality of predetermined current pulse shapes to be applied to the plurality of MTJs to induce generation of a probabilistic random bit.
4. The probabilistic random number generator of claim 1, wherein the current source further comprises:
an input current terminal coupled to the plurality of current paths, wherein the plurality of current paths branch off the input current terminal; an output current terminal coupled to a first subset of the plurality of current paths; and a ground terminal coupled to a second subset of the plurality of current paths.
12. The probabilistic random number generator of claim 10, wherein the current source further comprises: an input current terminal coupled to the plurality of current paths, wherein the plurality of current paths branch off the input current terminal; an output current terminal coupled to a first subset of the plurality of current paths; and a ground terminal coupled to a second subset of the plurality of current paths.
5. The probabilistic random number generator of claim 4, further comprising: an access transistor coupled between the MTJ and the output current terminal, the access transistor comprising a first source/drain region, a second source/drain region, and a gate disposed between the first and second source/drain regions, the first source/drain region of the access transistor being coupled to the MTJ and the second source/drain region of the access transistor being coupled to the output current terminal.
13. The probabilistic random number generator of claim 12, wherein a current path further comprises: an access transistor coupled between the MTJ of the current path and the output current terminal, the access transistor comprising a first source/drain region, a second source/drain region, and a gate disposed between the first and second source/drain regions, the first source/drain region of the access transistor being coupled to the MTJ and the second source/drain region of the access transistor being coupled to the output current terminal.
6. The probabilistic random number generator of claim 1, wherein the MTJ comprises: a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a ferromagnetic reference layer overlying the non-magnetic barrier layer.
14. The probabilistic random number generator of claim 1, wherein the MTJ comprises: a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a ferromagnetic reference layer overlying the non-magnetic barrier layer.
7. The probabilistic random number generator of claim 1, wherein the current source is configured to provide a current pulse shape to the MTJ to generate a probabilistic random bit, where the current pulse shape induces a switching probability for the MTJ that ranges between 5% and 95%.
See claim 1. “…the current pulse shape induces a switching probability for the MTJ that ranges between 5% and 95%...”
8. The probabilistic random number generator of claim 7, wherein the switching probability for the MTJ ranges between 10% and 90%.
2. The probabilistic random number generator of claim 1, wherein the switching probability for the MTJ ranges between 10% and 90%.
9. The probabilistic random number generator of claim 7, wherein the current source is configured to provide at least two different predetermined current pulse shapes in addition to the current pulse shape.
3. The probabilistic random number generator of claim 1, wherein the current source is configured to provide at least two different predetermined current pulse shapes in addition to the current pulse shape.
10. The probabilistic random number generator of claim 9, further comprising: a controller configured to select the current pulse shape from a set including the current pulse shape and the at least two different predetermined current pulse shapes to induce the MTJ to switch from a first data state to a second data state according to the switching probability.
4. The probabilistic random number generator of claim 3, further comprising: a controller configured to select the current pulse shape from a set including the current pulse shape and the at least two different predetermined current pulse shapes to induce the MTJ to switch from a first data state to a second data state according to the switching probability.
11. The probabilistic random number generator of claim 10 wherein a first current pulse shape of the at least two different predetermined current pulse shapes has a first amplitude and/or a first pulse width corresponding to a first switching probability of the MTJ switching from the first data state to the second data state, and wherein a second current pulse shape of the at least two different predetermined current pulse shapes has a second amplitude and/or a second pulse width corresponding to a second switching probability of the MTJ switching from the first data state to the second data state, the second switching probability differing from the first switching probability.
5. The probabilistic random number generator of claim 4: wherein a first current pulse shape of the at least two different predetermined current pulse shapes has a first amplitude and/or a first pulse width corresponding to a first switching probability of the MTJ switching from the first data state to the second data state, and wherein a second current pulse shape of the at least two different predetermined current pulse shapes has a second amplitude and/or a second pulse width corresponding to a second switching probability of the MTJ switching from the first data state to the second data state, the second switching probability differing from the first switching probability.
12. The probabilistic random number generator of claim 11, wherein the first amplitude and/or the first pulse width is less than the second amplitude and/or the second pulse width and the first switching probability is less than the second switching probability.
6. The probabilistic random number generator of claim 5, wherein the first amplitude and/or the first pulse width is less than the second amplitude and/or the second pulse width and the first switching probability is less than the second switching probability.
13. The probabilistic random number generator of claim 11, wherein the set further includes a third predetermined current pulse shape, which differs from the first current pulse shape and the second current pulse shape.
8. The probabilistic random number generator of claim 5, wherein the set further includes a third predetermined current pulse shape, which differs from the first current pulse shape and the second current pulse shape.
14. The probabilistic random number generator of claim 13: wherein the third predetermined current pulse shape has a third current amplitude and a third pulse width configured to switch the MTJ from the first data state to the second data state with at least 99.99% probability.
9. The probabilistic random number generator of claim 8: wherein the third predetermined current pulse shape has a third current amplitude and a third pulse width configured to switch the MTJ from the first data state to the second data state with at least 99.99% probability.
15. A probabilistic random number generator, comprising: a memory cell; a variable current source coupled to the memory cell; and a controller configured to write a probabilistic random data state to the memory cell by applying a predetermined current pulse shape to the memory cell.
19. A probabilistic random number generator, comprising: a memory cell comprising a variable resistor configured to switch between a first stable data state corresponding to a first resistance and a second stable data state corresponding to a second resistance, the second resistance differing from the first resistance; a variable current source coupled to the variable resistor; and a controller configured to write a probabilistic random data state to the variable resistor by applying a predetermined current pulse shape to the variable resistor, wherein the controller is configured to provide at least two different predetermined current pulse shapes in addition to the predetermined current pulse shape; wherein a first current pulse shape of the at least two different predetermined current pulse shapes has a first amplitude and/or a first pulse width corresponding to a first switching probability of the variable resistor switching from the first stable data state to the second stable data state, and wherein a second current pulse shape of the at least two different predetermined current pulse shapes has a second amplitude and/or a second pulse width corresponding to a second switching probability of the variable resistor switching from the first stable data state to the second stable data state, the second switching probability differing from the first switching probability.
16. The probabilistic random number generator of claim 15, wherein the memory cell comprising a variable resistor or a magnetic tunnel junction configured to switch between a first stable data state corresponding to a first resistance and a second stable data state corresponding to a second resistance, the second resistance differing from the first resistance.
See claim 19. “…a second switching probability of the variable resistor switching from the first stable data state to the second stable data state, the second switching probability differing from the first switching probability…”
17. The probabilistic random number generator of claim 16, wherein the predetermined current pulse shape is configured to switch the memory cell from the first stable data state to the second stable data state with a probability of between 5 % and 95 %.
20. The probabilistic random number generator of claim 19, wherein the predetermined current pulse shape is configured to switch the variable resistor from the first stable data state to the second stable data state with a probability of between 5% and 95%.
18. A method of generating a bitstream of data comprising probabilistic random bits, comprising:
providing a memory cell in a first data state; and selecting a first predetermined current pulse shape from a plurality of predetermined current pulse shapes, and applying the first predetermined current pulse shape to the memory cell when the memory cell is in the first data state, wherein the predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities to switch the memory cell from the first data state to a second data state.
15. A method of generating a bitstream of data comprising probabilistic random bits, comprising: providing a magnetic tunnel junction (MTJ) in a first stable data state; and applying a first predetermined current pulse shape to the MTJ when the MTJ is in the first stable data state; wherein the first predetermined current pulse shape induces the MTJ to output a probabilistic random bit; applying a second predetermined current pulse shape to the MTJ, the second predetermined current pulse shape having a second current amplitude and a second pulse width configured to switch the MTJ from the first stable data state to a second stable data state with at least 99.99% probability.
19. The method of claim 18, further comprising: applying a second predetermined current pulse shape to the memory cell, the second predetermined current pulse shape having a second current amplitude and a second pulse width configured to switch the memory cell from the first data state to the second data state with at least 99.99 % probability.
See claim 15. “…the second predetermined current pulse shape having a second current amplitude and a second pulse width configured to switch the MTJ from the first stable data state to a second stable data state with at least 99.99% probability.”
20. The method of claim 19, further comprising: applying a third predetermined current pulse shape to the memory cell, the third predetermined current pulse shape having a third current amplitude and a third pulse width configured to switch the memory cell from the second data state to the first data state with at least 99.99 % probability.
17. The method of claim 15, further comprising: applying a third predetermined current pulse shape to the MTJ, the third predetermined current pulse shape having a third current amplitude and a third pulse width configured to switch the MTJ from the second stable data state to the first stable data state with at least 99.99% probability.
As can be seen from the above table, similar to the patent, claim 1 of the application recites a probabilistic random number generator comprising a memory cell and current source coupled to the MTJ, wherein the current source comprising a plurality of current paths and a plurality of MTJs on the plurality of current paths, respectively. Unlike the patent, the application recites that the current paths are disposed in parallel with one another; however, one of ordinary skill in the art would recognize that if a current source has a plurality of current paths with each MTJ on respective current paths, the paths are parallel to one another since they are forming the necessary structure. Therefore, coverage have already been given to the prior patent.
Similar to the patent, claim 15 of the application recites a probabilistic random number generator comprising a memory cell, a variable current source coupled to the memory cell and a controller to write data to the memory cell. Unlike the patent, the application does not indicate that the current source is a resistor and the way in which the controller writes using the state of the resistor. However, it is reasonable to interpret that the resistor can be a current source. Additionally, since the claim of the patent is more limited, it would encompass all limitations of the claim of the present application. Therefore, the patent protections have been granted to the earlier filed patent application.
Similar to the patent, claim 18 of the application recites a method of generating a bitstream of data comprising probabilistic random bits comprising providing a first data state and applying predetermined current pulse shape. Unlike the patent, the application recites the providing a first data state to a memory cell; whereas, the patent recites that it's directed to an MTJ. However, it is reasonable to state that the two concepts are similar, in that both are memory cells. Additionally, since the claim of the patent is more limited, it would encompass all limitations of the claim of the present application. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-14, 16, 17, 19 and 20 are rejected over claims 1-6, 8-15, 17, 19 and 20 of patent ‘153.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda et al. [US Patent Application # 20090201717].
With respect to claim 1, Maeda et al. disclose a probabilistic random number generator, comprising: a memory cell [10 of fig. 1] comprising a magnetic tunnel junction (MTJ) [MTJ]; and a current source [interpreting L1 and L2 as one entity] coupled to the MTJ, wherein the current source comprises: a plurality of current paths [paths coupling to L2 electrode via BL1] disposed in parallel with one another; and a plurality of MTJs [REF1 and REF2] on the plurality of current paths, respectively.
With respect to claim 2, Maeda et al. disclose a plurality of transistors [Tr1 and Tr2] arranged on the plurality of current paths, respectively, wherein each current path includes a respective transistor and a respective MTJ arranged in series on that current path [see fig. 1].
With respect to claim 6, Maeda et al. disclose the MTJ comprises: a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a ferromagnetic reference layer overlying the non-magnetic barrier layer [“…The MTJ element MTJ includes a pinned layer p in which the magnetization direction is fixed, a free layer f in which the magnetization direction changes in accordance with the direction of a write current, and a nonmagnetic layer n sandwiched between the pinned layer p and free layer f.” – par. 0041].
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oishi et al. [US Patent Application # 20110123022].
With respect to claim 15, Oishi et al. disclose a probabilistic random number generator [2 and 3 of fig. 1a], comprising: a memory cell [anyone of 3a]; a variable current source [“…the temperature control circuit 39 checks the influence of the external environment from the read signal intensity, and adjusts the current so that the writing probability may become 1/2 (step S15) to store the value of the adjusted current in the memory 40.” – par. 0068] coupled to the memory cell [39 and 40 coupled to 3a via 33 and 34 – see fig. 3]; and a controller [37] configured to write a probabilistic random data state to the memory cell by applying a predetermined current pulse shape to the memory cell [“…the writing probability in the negative direction with a pulse width of 25 ns.“ – par. 0080].
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aparin [US Patent Application # 20130117209].
With respect to claim 18, Aparin disclose a method of generating a bitstream of data comprising probabilistic random bits, comprising: providing a memory cell [fig. 3] in a first data state [either low resistance or high resistance shown in fig. 3]; and selecting a first predetermined current pulse shape from a plurality of predetermined current pulse shapes [“…the module 202 may be configured to compute the synaptic weight update 204 for each weight according to the chosen learning rule…” – par. 0038; not that the cited section indicates that there are multiple rules to be selected, which would produce respective pulses 208 to be applied to memory 210], and applying the first predetermined current pulse shape to the memory cell [208 to 210] when the memory cell is in the first data state [“…an interface module 206 may be configured to generate, with a certain probability, a signal 208 (e.g., a pulse) based on the update of weight 204. For example, a sign of the pulse (positive or negative pulse) may correspond to a sign of the weight update 204. A binary state of memory location within a memory 210 representing that particular weight may be switched (i.e., changed from zero to one, or vice versa) based on the pulse 208.” – par. 0032], wherein the predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities to switch the memory cell from the first data state to a second data state [“…a switching probability in an STT memory as a function of current (pulse) amplitude and write time.” – pars. 0032 and 0037].
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claim 16 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Oishi et al. [US Patent
Application # 20110123022] in view of Aparin [U.S. Patent Application # 20130117209].
Oishi et al. disclose a probabilistic random number generator [2 and 3 of fig. 1a], comprising: a memory cell [anyone of 3a]; a variable current source [“…the temperature control circuit 39 checks the influence of the external environment from the read signal intensity, and adjusts the current so that the writing probability may become 1/2 (step S15) to store the value of the adjusted current in the memory 40.” – par. 0068] coupled to the memory cell [39 and 40 coupled to 3a via 33 and 34 – see fig. 3]; and a controller [37] configured to write a probabilistic random data state to the memory cell by applying a predetermined current pulse shape to the memory cell [“…the writing probability in the negative direction with a pulse width of 25 ns. “ – par. 0080].
Oishi et al. discloses all of the above mentioned, specifically, the memory cell being a nonvolatile memory [par. 0031] but is silent about the memory cell comprising a variable resistor or a magnetic tunnel junction configured to switch between a first stable data state corresponding to a first resistance and a second stable data state corresponding to a second resistance, the second resistance differing from the first resistance. However, this is not new. Aparin discloses the application of the MTJ as a nonvolatile memory cell capable of switching between two data states corresponding to two resistance states [“…the probabilistic nonvolatile binary memory may be based on magnetic tunnel junction (MTJ) or spin torque transfer (STT) devices. These devices can act as binary resistive switches whose switching from one state to another is a probabilistic event with the probability being a function of the write current/voltage magnitude and duration, as illustrated in FIG. 3. In examples 302, 304, a passing current 306 may be used to switch direction of magnetization. As illustrated in FIG. 3, the binary zero may be stored in a location of the STT memory if direction of magnetization is in a parallel state (i.e., the current 306 may flow easily though ferromagnetic layers because of a low resistance). On the other hand, the binary one may be stored in the memory location if direction of magnetization is in an anti-parallel state (i.e., the current 306 may flow with certain difficulties though ferromagnetic layers due to a high resistance)” – par. 0034]. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the Oishi et al. memory circuit element to include the element as taught by Aparin, since the modification is merely a substitution of a functionally recognized equivalent element.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 6, 2026