DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/3/2024, 2/22/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 12-14, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20190074304 A1)
Regarding claim 1, Lee discloses (Fig. 8) A display device (¶ [0002]) comprising: a substrate (100); a first transistor (TFT1, Fig. 8) comprising:
a first active layer (211) disposed on the substrate and comprising: a first portion (middle SCL) comprising a first channel region (middle SCL), and a second portion (211s, left BGL, left SCL) and a third portion (right BGL, right SCL, 211d) spaced apart from each other with the first portion disposed between the second portion and the third portion, and a first gate electrode (middle 213g) disposed on the first portion of the first active layer; at least one first dummy gate electrode (left 213g, right 213g) disposed on a part of at least one of the second portion or the third portion of the first active layer and spaced apart from the first gate electrode; and a first gate insulating layer (120) disposed between the first active layer and each of the first gate electrode and the at least one first dummy gate electrode.
Regarding claim 12, Lee discloses the display device of claim 1, further comprising (Fig. 8): a pixel comprising a pixel circuit (TFT1) comprising the first transistor and a light emitting element connected to the pixel circuit, wherein the first transistor is a driving transistor (¶ [0049]) which controls a driving current flowing through the light emitting element in response to a voltage applied to the first gate electrode.
Regarding claim 13, Lee discloses the display device of claim 12, wherein (Fig. 8) the at least one first dummy gate electrode comprises a plurality of first dummy gate electrodes (left, right 213g), and the plurality of first dummy gate electrodes are disposed at sides of the first gate electrode and disposed above each of the second portion and the third portion of the first active layer.
Regarding claim 14, Lee discloses the display device of claim 12, wherein (Fig. 8) the pixel circuit further comprises a second transistor (TFT2, Fig. 2) electrically connected to the first gate electrode, and the second transistor comprises: a second active layer (217) disposed on the substrate, and comprising: a first portion (217a) comprising a second channel region, a second portion (217s) disposed at a side of the second channel region and comprising a second source region, and a third portion (217d) disposed at another side of the second channel region and comprising a second drain region; and a second gate electrode (G2) disposed on the first portion of the second active layer.
Regarding claim 19, Lee discloses the display device of claim 14, wherein the first active layer and the second active layer include an oxide semiconductor (TFT1, TFT2 are MOSTFT, ¶ [0096])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190074304 A1) in view of Park (US 20010028058 A1)
Regarding claim 2, Lee discloses the display device of claim 1 but is silent regarding the first gate insulating layer comprises a first insulating pattern layer disposed between the first active layer and the first gate electrode, and exposes a part of each of the second portion and the third portion of the first active layer.
Park discloses (Fig. 6A, ¶ [0037]) a thin film transistor having an active layer (51) with a first portion (51c), a second portion (left 56, left 51c’, 51a) and a third portion (right 56, right 51c’, 51b), patterned gate insulator (52) and gate electrodes (53, left 54, right 54) wherein the patterned gate insulator exposes the second and third portions.
Artisans in the art would have appreciated a patterned gate insulator is not uniform across the gate surface but is shaped and segmented to match the transistor’s geometry, and thus ensuring uniform electric field distribution and consistent gate control over the active channel. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to adapt the continuous gate insulator of Lee for the patterned gate insulator of Park to achieve uniform electric field distribution between the gate and the channel. Doing so would help improve the uniformity of the electric field between the gate and the channel and ensure consistent control of the channel’s conductivity across its entire length.
Regarding claim 3, Lee in view of Park discloses the display device of claim 2. Park further discloses (Fig. 5, ¶ [0037]) wherein the first gate insulating layer further comprises a second insulating pattern layer disposed between the at least one first dummy gate electrode and the first active layer.
Regarding claim 16, Lee discloses the display device of claim 15. The modified structure of the display device would allow the second transistor to have the same multi-gate structure as the first transistor. As such the modified second transistor of Fig. 8 would have the second gate insulating layer disposed between the active channel layer and the gate electrodes. However, Lee is silent regarding the second gate insulating layer exposes a part of each of the second portion and the third portion of the second active layer, and the second gate electrode covers at least the second channel region, and overlaps a part of each of the second source region and the second drain region around the second channel region.
Park discloses (Fig. 6A, ¶ [0037]) a thin film transistor having an active layer (51) with a first portion (51c), a second portion (left 56, left 51c’, 51a) and a third portion (right 56, right 51c’, 51b), patterned gate insulator (52) and gate electrodes (53, left 54, right 54) wherein the patterned gate insulator exposes the second and third portions.
Artisans in the art would have appreciated a patterned gate insulator is not uniform across the gate surface but is shaped and segmented to match the transistor’s geometry, and thus ensuring uniform electric field distribution and consistent gate control over the active channel. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to adapt the continuous gate insulator of Lee for the patterned gate insulator of Park to achieve uniform electric field distribution between the gate and the channel. Doing so would help improve the uniformity of the electric field between the gate and the channel and ensure consistent control of the channel’s conductivity across its entire length.
Claim(s) 4-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190074304 A1) in view of Tanaka (US 20010010702 A1)
Regarding 4, Lee discloses the display device of claim 1. Lee further discloses (Fig. 8) wherein the first active layer further comprises: a first source region (211s, left BGL) disposed in the second portion and disposed at a side of the first channel region, and a first drain region (right BGL, 211d) disposed in the third portion and disposed at another side of the first channel region, and the first gate electrode covers at least the first channel region.
Lee is silent regarding the first gate electrode overlaps a part of the first source region and a part of the first drain region by a first length in a longitudinal direction of the first active layer.
Tanaka discloses (Fig. 16B, ¶ [0236]) a first gate (middle 247), a first source region (249a, 249b, 249c, 250a, 250b, 250c), a first drain region (251a, 251b, 251c, 252a, 252b, 252c) and the first gate overlapping a part of the first source and a part of the drain region with a first length (250c and a portion of 251a)
Regarding claim 5, Lee in view of Tanaka discloses the display device of claim 4. Though Tanaka is silent regarding wherein the first dummy gate electrode (Tanaka: left 247, Fig. 16B) has a length less than or equal to the first length in the longitudinal direction of the first active layer, Tanaka’s first dummy gate appears greater than the first length. Artisans in the art would have appreciated the gate length of the dummy gate in multi-gate thin film transistors plays a critical role in both fabrication fidelity and device performance. As such where the general conditions (the size of dummy gates compared to the first length (total overlapping portions of main gate over source region and drain region)) of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges (first dummy gate length shorter or equal to the first length) through routine experimentation. As such it would have been obvious to one of ordinary skill in art before the filing date of the invention to select the dummy gate length to be shorter or equal to the total overlapping length of the main gate on the source and drain regions for a diversity of device applications.
Regarding claim 6, Lee in view of Tanaka discloses the display device of claim 4. Tanaka discloses (Fig. 16B) the first dummy gate electrode (left 247) has a length longer than the first length in the longitudinal direction of the first active layer, and the first active layer further comprises at least one dummy channel region (246a) disposed in at least one of the second portion or the third portion and overlapping the first dummy gate electrode.
Regarding claim 7, Lee in view of Tanaka discloses the display device of the display device of claim 6, wherein the first dummy gate electrode covers the dummy channel region, and overlaps a part of the first source region (249c) or a part of the first drain region (250a) around the dummy channel region.
Regarding claim 8, Lee in view of Tanaka discloses the display device of claim 7, wherein the dummy channel region has a short channel (246a) such that a dummy transistor comprising the first dummy gate electrode and the dummy channel region operates in a threshold voltage roll-off region (channel length 3-7µm, ¶ [0236], the operation threadhold voltage is intended use and it does not alter the structure of the dummy channel region).
Regarding claim 9, Lee in view of Tanaka discloses the display device of claim 7. Lee discloses further comprising: a pixel (PX, Fig. 2) comprising a plurality of pixel transistors comprising the first transistor (PX, Fig. 2) wherein the dummy channel region has a length shorter than a length of a channel region of each of the plurality of pixel transistors (dummy channel region is part of the pixel channel region).
Regarding claim 10, Lee in view of Tanaka discloses the display device of claim 4. Lee further discloses (Fig. 8) comprising: an interlayer insulating layer (140) disposed on the substrate, and covering the first active layer, the first gate insulating layer, the first gate electrode and the first dummy gate electrode, wherein the first transistor further comprises at least one of a first source electrode disposed on the interlayer insulating layer and electrically connected to the first source region, or a first drain electrode disposed on the interlayer insulating layer and electrically connected to the first drain region (Fig. 8).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190074304 A1) in view of Kim (US 20250275117 A1)
Regarding claim 11, Lee discloses the display device of claim 1, but is silent regarding further comprising: a power line electrically connected to the first dummy gate electrode and to which a gate-on voltage of the first transistor is applied.
Kim discloses (Fig. 1A, ¶ [0032]) a multigate transistor may have voltage applied to a sub-gate to perform channel operation. Artisans in the art would have appreciated that in multi-gate structures, the channel is surrounded by more than one gate electrodes and each gate can be biased independently or in combination to perform channel operation. As such one of ordinary skill in the art before the effective filing date of the invention would have adopted the teaching of Kim to the multi-gate structure of Lee to apply voltage to a dummy gate electrode to control the channel operation. Doing so would allow for the transistor to have multiple potentials from multiple directions.
Claim(s) 15, 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Lee (US 20190074304 A1)
Regarding claim 15, Lee discloses the display device of claim 14. Lee is silent regarding wherein the pixel further comprises: at least one second dummy gate electrode disposed on a part of at least one of the second portion or the third portion of the second active layer, and spaced apart from the second gate electrode; and a second gate insulating layer comprising insulating pattern layers disposed between the second active layer and each of the second gate electrode and the at least one second dummy gate electrode.
While being silent to the second transistor being a multi-gate transistor, Lee discloses the first driving transistor as the multi-gate transistor. As such, where the general conditions (multi-gate transistor) of a claim are disclosed in the prior art, it is not inventive to discover the optimal or workable ranges (second transistor as a multi-gate transistor) by routine experimentation. MPEP 2144.05
Artisans in the art would have appreciated that mirroring transistor structures would optimize layout and increase uniformity across the device ensuring predictable electrical performance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the second transistor of Lee such that it mirrors the structure of the first transistor. Doing so would enhance the system symmetrical and predictable electrical performance.
Regarding claim 17, Lee discloses the display device of claim 15. The modified structure of the second transistor in Fig. 8 of Lee would result for the second transistor to have the multi-gate structure as the first transistor; As such the second dummy gate electrode can have similar structure like the first dummy gate electrode (Fig. 8) wherein the at least one second dummy gate electrode (left, right 213g) comprises a plurality of second dummy gate electrodes (left, right 213g), and the plurality of second dummy gate electrodes are disposed at sides of the second gate electrode and disposed above each of the second portion (211s, left SCL, left BGL) and the third portion (right BGL, right SCL, 211d) of the second active layer.
Regarding claim 18, Lee discloses the display device of claim 15, wherein the second source region is electrically connected to the first gate electrode (Fig. 2). The modified second transistor of Lee does not disclose the pixel comprises a single second dummy gate electrode disposed only on the second portion of the second active layer.
While the modified second transistor can be the multi-gate transistor like the first transistor which has dummy gates disposed on the second portion and third portions of the second active layer. However, where the general conditions (multi-gate structures) of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges (the number of dummy gate) by routine experimentation. MPEP 2144.05
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the number of dummy gate to include only one dummy gate on the second portion of the second active layer for a diversity of applications.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20010028058 A1) in view of Lee (US 20190074304 A1)
Regarding claim 20, Park discloses A method of manufacturing a display device (¶ [0019]), the method comprising: forming an active layer (51, Fig. 6A, ¶ [0037]); forming a gate insulating layer (first insulating layer, ¶ [0037]) covering the active layer on the substrate; forming insulating pattern layers (patterned 52, Fig. 6A, ¶ [0037]) under each of the gate electrode and the at least one dummy gate electrode, and exposing a part of the active layer which does not overlap the gate electrode and the at least one dummy gate electrode;
forming, on the gate insulating layer, a gate electrode (53, ¶ [0037]) and at least one dummy gate electrode (54) which overlap different parts of the active layer and are spaced apart from each other (Fig. 6A, ¶ [0037]); forming an interlayer insulating layer (57, Fig. 6D, ¶ [0043]) covering the active layer, the insulating pattern layers, the gate electrode and the at least one dummy gate electrode.
While not disclosing the patterning of the gate insulating layer is done by etching, Park discloses the masking and etching as examples of patterning and removing portions of layers to the predetermined patterns (¶ [0038]). As such where the general conditions (masking and etching method) of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges (etching the gate insulating layer to a predetermined patterns) by routine experimentation. MPEP 2144.05. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the etching method to pattern the gate insulating layer of Park to predetermined patterns for a diversity of applications.
Park is silent regarding the thin film transistor used as a pixel switching circuit (¶ [0025]) including an oxide semiconductor layer as part of the active layer. Lee discloses the method of fabricating a display (¶ [0013]) including using a thin film transistor (TFT1, TFT2, Fig. 8) as the pixel driving circuit (¶ [0049]) and the thin film transistor may be a MOSFET (¶ [0096]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute a MOSFET of Lee for the FET of Park to be used as a pixel driving circuit for a diversity of application.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Konuma (US 6833560 B2) discloses a display using a double or triple gate structure as the pixel driving circuit.
Conclusion
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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