Prosecution Insights
Last updated: October 21, 2026
Application No. 18/763,990

TEMPERATURE CONTROL METHOD FOR SEMICONDUCTOR PROCESS

Non-Final OA §102§103
Filed
Jul 03, 2024
Priority
Jul 14, 2023 — CN 202310871362.7
Examiner
SYLVIA, CHRISTINA A
Art Unit
Tech Center
Assignee
Beijing E-Town Semiconductor Technology Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
680 granted / 776 resolved
+27.6% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
22 currently pending
Career history
805
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
58.9%
+18.9% vs TC avg
§102
23.4%
-16.6% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 776 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Foreign Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 08/19/2024. Information Disclosure Statement The information disclosure statements (IDS) submitted on 05/16/2025 and 01/07/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Drawings Figure 1 and figure 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claim(s) 1-4 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo (TW 421832B; as supplied in IDS dated 01/07/2025.). PNG media_image1.png 508 334 media_image1.png Greyscale Regarding claim 1, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches a temperature control method for semiconductor process, comprising: setting a first measurement point (temperature probe point) of a first point distribution (concentric circular array points; see Fig. 3) in a first process device (RTA chamber) to measure a temperature in the first process device (“to effectively control the temperature distribution in the rapid heating process, traditionally, a plurality of probes (probes) for detecting the intensity of thermal radiation energy are installed in the rapid heating equipment of the wafer to measure the temperature at a specific position of the wafer. Distribution conditions and adjust the output function of the heating lamp through the probes at these specific positions.”); and setting a second measurement point (second measurement probe site) of a second point distribution in a second detection device (heat lamp device) to measure a target parameter (temperature and/or wafer thickness); wherein the first point distribution comprises a concentric circle-shaped dot matrix with unequal radial spacings (see Fig. 3 and Fig. 4); and the second point distribution has a concentric circle-shaped dot matrix corresponding to the first point distribution (see Fig. 3 and Fig. 4). Regarding claim 2, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches concentric circles (4 depicted in Fig. 3) of the first point distribution (probe points 1-40 of Fig. 3) correspond to heating regions of the first process device one by one (RTA chamber); and concentric circles of a measurement dot matrix correspond to the plurality of heating regions respectively (see Fig.3 and Fig. 4). Regarding claim 3, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches obtaining a process temperature of each point of a tested semiconductor workpiece in the first point distribution under a standard process condition in the first process device (the temperature associated with each probe point 1-40 of Fig. 3); detecting a target parameter of the tested semiconductor workpiece corresponding to the process temperature (table value) and determining a corresponding relationship between the process temperature and the target parameter in the second detection device (see note below); detecting a target parameter of a semiconductor workpiece to be tested (temperature or thickness) and comparing a measured value of the target parameter of the semiconductor workpiece to be tested with a set standard range of the target parameter in the second detection device (see note below); calculating a deviation value of the target parameter if the measured value of the target parameter of the semiconductor workpiece to be tested exceeds the set standard range (using the equation noted below); calculating a temperature deviation value in each heating region from the deviation value of the target parameter according to the corresponding relationship; and performing temperature compensation on each heating region according to the temperature deviation value in each heating region (see note below). Note: “Please refer to FIG. 5 for the method proposed by the present invention. It is represented by a flow chart. As shown in the figure, the wafer is first placed in a rapid heating equipment for heat treatment 'as shown in step 502. Then the wafer is taken out from the rapid heating equipment, and the wafer is measured in a circular manner. Surface temperature-dependent characteristic values (ie resistance, thickness, etc.), as in step 504. The characteristic values in each ring-shaped sampling area are averaged, as shown in step 506. The average of eigenvalues' calculates the characteristic value of the probe at each position, as in step 508. Then find the characteristics of the probe The distance between the value and the target value, and divides the distance value by the sensitivity of the corresponding material sign value to obtain the temperature correction parameters of each probe, as shown in ㈣51Q *. Then, obtain the temperature correction parameters obtained. Adjust the heating temperature distribution status of the rapid heating equipment, as in step 51 4. Then determine whether the characteristic value distribution of the surface of the wafer falls within an acceptable range, and if so, end this calibration adjustment process, such as step 5丨 6; ^ No, return to step 5 2 and continue to adjust the heating temperature distribution process of the rapid heating equipment until the result falls within an acceptable range”. Regarding claim 4, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches the temperature compensation is performed by adjusting power of a heating element of each heating region. (“In order to provide a method for adjusting the heating temperature distribution on the surface of the wafer during the heat treatment process. The present invention discloses a method for adjusting the surface temperature distribution of a wafer in a semiconductor heat treatment system. First, the wafer is placed in a heat treatment system for heat treatment. The circle is taken out from the heat treatment system, and the temperature-dependent characteristic value of the wafer surface is measured by a circular sampling method on the wafer surface to measure (resistance value, thickness, etc). Then the temperature-dependent characteristic value of the heavy item is combined with the numerical calculation method to find the temperature-dependent characteristic values of the probes at different positions in the heat treatment preparation station and the cooling system. Subtract the target values from the probe-dependent temperature-dependent characteristic values of these probes, and then divide by Corresponds to the sensitivity of the temperature-dependent characteristic value of the temperature and temperature, to obtain the temperature correction gray and U parameters at each probe position, and finally use these temperature correction parameters to adjust the heating system heating The temperature distribution situation at the time.”) Regarding claim 6, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches the first process device is a rapid thermal annealing device, and the semiconductor workpiece processed is a wafer (refer to Fig. 3; “The first circle, the second circle, the third circle, the fourth circle, and the fifth circle are schematic sectional views of a rapid heating device. It is a schematic diagram of measuring the surface resistance value of a wafer by a one-dimensional ring method in the present invention. This is a schematic diagram of Yin's calculation of the wafer surface resistance values at different probe positions using interpolation.”). Regarding claim 7, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches the rapid thermal annealing device (see Fig. 1) comprises a plurality of heating lamp groups and comprises a plurality of heating regions. (“In order to effectively control the temperature distribution in the rapid heating process, traditionally, a plurality of probes (probes) for detecting the intensity of thermal radiation energy are installed in the rapid heating equipment of the wafer to measure the temperature at a specific position of the wafer. Distribution conditions and adjust the output function of the heating lamp through the probes at these specific positions.”) Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 2. Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Guo, as applied to claim 1 above, and further in view of Applicants own Admitted Prior Art (hereinafter AAPA). Regarding claim 10, refer to Fig. 1, Fig. 5 and Fig. 3-Fig.4 (provided above), Guo teaches when the semiconductor workpiece (wafer) processed is an 8” inch wafer (aka 200mm), the first point distribution comprises a center point, and a concentric circle-shaped dot matrix (see Fig. 3) extending radially outward from the center point at distances of 25.4mm, 41.4mm, 57.5mm, 82.6mm and 95mm (non-uniform; see Fig.3). Although, Guo teaches the non-uniform distribution of the coencentric circle shaped dot matrix he does not teach this as being applied to a 12” wafer”; wherein the concentric circle-shaped dot matrix (see Fig. 3) extending radially outward from the center point at distances of “25 mm, 60 mm, 80 mm, 110 mm, 120 mm and 147 mm respectively.” PNG media_image2.png 354 454 media_image2.png Greyscale In the same field of endeavor, refer to Fig. 3-provided above, AAPA teaches a method of measuring a concentric wafer heart distribution comprising: a 12” wafer; wherein the 12” wafer comprises concentric circle-shaped dot matrix extending radially outward from the center point at equal distances. In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to increase the 8” wafer of Guo, to the 12” wafer size as taught by AAPA, while increasing the concentric circles non-uniformly to increase the device yield; while maintaining the testing parameters as taught by Guo. Prior Art 3. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: a. Shimazu et al. (US Patent No. 6,577,927) teaches method of detecting and controlling in-situ faults in rapid thermal processing systems. b. Kuwahara et al. (PG Pub 2018/0218935) heating apparatus is configured to mount substrate on a mounting table and heat substrate, heating apparatus comprises multiple heaters which are provided in mounting table and heat generation amounts of which are controlled independently. c. Lee et al. (PG Pub 2024/0186161) teaches substrate processing method, thermal processing apparatus, and semiconductor manufacturing equipment. Allowable Subject Matter 4. Claims 5 and 8-9 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 5 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 5, the target parameter is a square resistivity or a thickness of a surface oxide film of the semiconductor workpiece. Claim 8 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 8, the corresponding relationship determines a rate of change through a change in the target parameter detected in the second detection device when the process temperature in the first process device changes by 1°C. Claim 9 would be allowable, because it depends on allowable claim 8 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Jul 03, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.6%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 776 resolved cases by this examiner. Grant probability derived from career allowance rate.

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