DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation (emphasis added), "a thickness of the first portion of the first word line trench is greater than a thickness of the second portion of the first word line trench." in lines 5-7. There is insufficient antecedent basis for this limitation in the claim. Due to their dependency, claims 13 and 14 are also rejected.
The examiner believes that the above phrase should read: a thickness of the first portion of the gate dielectric layer is greater than a thickness of the second portion of the gate dielectric layer. For purposes of examination, the examiner has interpreted claim 12 and dependent claims 13 and 14 in this manner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (United States Patent Application Publication No. US 2018/0190661 A1, hereinafter “Wang”).
In reference to claim 1, Wang discloses a device which meets the claim. Fig. 1 of Wang discloses a memory structure which comprises a substrate (16) having a source/drain implant region (40). A first word line (30, 32) is within the substrate (16) and across the source/drain implant region (40). The first word line (30, 32) comprises a gate dielectric layer (30). The gate dielectric layer (30) comprises a first portion (42) in the source/drain implant region (40) and a second portion (44) out of the source/drain implant region (40). A thickness of the first portion (42) of the gate dielectric layer (30) is greater than a thickness of the second portion (44) of the gate dielectric layer (30).
With regard to claim 2, the first word line (30, 32) comprises a gate structure (34, 36) over the gate dielectric layer (30).
In reference to claim 3, a dielectric cap (38) covers the gate structure (34, 36).
With regard to claim 4, the gate structure (34, 36) is enclosed by the gate dielectric layer (30) and the dielectric cap (38) in a cross-section.
In reference to claim 6, the first portion (42) of the gate dielectric layer (30) comprises an inclined sidewall.
With regard to claim 7, the first portion (42) of the gate dielectric layer (30) further comprises a vertical sidewall extending from a top surface of the substrate (16). The inclined sidewall of the first portion (42) of the gate dielectric layer (30) is connected between the vertical sidewall of the first portion (42) of the gate dielectric layer (30) and the second portion (44) of the gate dielectric layer (30).
In reference to claim 8, fig. 1 of Wang shows the memory in a plan view while fig. 2 is the cross-section along line A-A’. The first word-line (30, 32) of fig.2 is the leftmost word-line (14,22) in fig. 1. Fig. 1 shows that there is a second word line (14, 22 – second from the left) across the source/drain implant region (18 – in fig. 1). Fig. 1 shows a bit line (12) that is over the substrate (16) and between the first and second word lines.
With regard to claim 9, fig. 1 of Wang shows the memory in a plan view while fig. 2 is the cross-section along line A-A’. The first word-line (30, 32) of fig.2 is the leftmost word-line (14,22) in fig. 1. Fig. 1 shows that there is a second word line (14, 22 – second from the left). Wang discloses (p. 1, paragraph 11) that the second word line (14, 22 – second from the left) is across an isolation area (STI, 24) of the substrate (16). Although not shown in the fig. 1 and 2, Wang discloses (p. 1, paragraph 12) that a capacitor structure is over the substrate (16) and between the first (14,22 – leftmost in fig. 1) and second word lines (14, 22- second from the left in fig. 1).
In reference to claim 10, Wang discloses (p. 1-2, paragraph 14) performing an oxidation process such that the first portion (42) of the gate dielectric layer (30) comprises an oxidized material of the source/drain implant region (40).
Claims 1-7 and 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (United States Patent Application Publication No. US 2009/0127609 A1, hereinafter “Han”).
In reference to claim 1, Han discloses a device which meets the claim. Fig. 1-11 of Han disclose a memory structure which comprises a substrate (51) having a source/drain implant region (81). A first gate (75, 77) is within the substrate (51) and across the source/drain implant region (81). Han does not explicitly disclose that the gate is a word line but this is understood to be the case since the transistor of fig. 1-11 is part of a DRAM (p. 4, paragraphs 44-45) connected to a bit line (87) and a capacitor (93). Thus the first gate (75, 77) is a first word line (75, 77) which comprises a gate dielectric layer (75). The gate dielectric layer (75) comprises a first portion in the source/drain implant region (81) and a second portion out of the source/drain implant region (81). Han discloses (p. 4-5, paragraph 52) that a thickness (D6) of the first portion of the gate dielectric layer (75) is greater than a thickness (D5) of the second portion of the gate dielectric layer (75).
With regard to claim 2, the first word line (75, 77) comprises a gate structure (77) over the gate dielectric layer (75).
In reference to claim 3, a dielectric cap (78) covers the gate structure (77).
With regard to claim 4, the gate structure (77) is enclosed by the gate dielectric layer (75) and the dielectric cap (78) in a cross-section.
In reference to claim 5, a width of the first portion of the gate dielectric layer (75) is less than a width of the second portion of the gate dielectric layer (75).
With regard to claim 6, the first portion of the gate dielectric layer (75) comprises an inclined sidewall at the corners where the upper trench (61’) meets the lower trench (71’).
In reference to claim 7, the first portion of the gate dielectric layer (75) further comprises a vertical sidewall extending from a top surface of the substrate (51). The inclined sidewall of the first portion of the gate dielectric layer (75) is connected between the vertical sidewall of the first portion of the gate dielectric layer (75) and the second portion of the gate dielectric layer (75).
With regard to claim 10, the first portion of the gate dielectric layer (75) is formed by oxidation (p. 4, paragraph 51) in the region of the substrate (51) that is implanted (p. 4, paragraph 41) to form the source/drain implant region (81).
In reference to claim 11, fig. 1-11 of Han disclose a memory structure which comprises a substrate (51) having a source/drain implant region (81). A first gate trench (61’, 71’) extends from a top surface of the substrate (51) and through the source/drain implant region (81). Han does not explicitly disclose that the first gate trench (61’, 71’) is a word line trench but this is understood to be the case since the transistor of fig. 1-11 is part of a DRAM (p. 4, paragraphs 44-45) connected to a bit line (87) and a capacitor (93). Thus the first gate trench (61’, 71’) is a first word line trench (61’, 71’). The first word line trench (61’, 71’) has an inclined sidewall at the corners where the upper trench (61’) meets the lower trench (71’) such that the entirety of the inclined sidewall is in the source/drain implant region (81) in a cross-section. A first word line structure (75, 77) is in the first word line trench (61’, 71’).
So far as understood in claim 12, a gate dielectric layer (75) is in the first word line trench (61’, 71’). The gate dielectric layer (75) has a first portion over the inclined sidewall of the first word line trench (61’, 71’) and a second portion lower than the source/drain implant region (81). Han discloses (p. 4-5, paragraph 52) that a thickness (D6) of the first portion of the gate dielectric layer (75) is greater than a thickness (D5) of the second portion of the gate dielectric layer (75).
So far as understood in claim 13, a material of the first portion of the gate dielectric layer (75) is formed by oxidation (p. 4, paragraph 51) in the region of the substrate (51) that is implanted (p. 4, paragraph 41) to form the source/drain implant region (81).
So far as understood in claim 14, a gate structure (77) is over the gate dielectric layer (75). A dielectric cap (78) is over the gate structure (77).
In reference to claim 15, the substrate (51) comprises a plurality of isolation areas (53) and a plurality of active areas (52) between the isolation areas (53). The source/drain implant region (81) is in one of the active areas (52).
Claims 11 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (United States Patent Application Publication No. US 2019/0067293 A1, hereinafter “Lin”).
In reference to claim 11, fig. 7-14 of Lin disclose a memory structure which comprises a substrate (60) having a source/drain implant region (66). A first word line trench (64, 74) extends from a top surface of the substrate (60) and through the source/drain implant region (66). The first word line trench (64, 74) has an inclined sidewall such that the entirety of the inclined sidewall is in the source/drain implant region (66) in a cross-section. A first word line structure (78, 84, 86, 88) is in the first word line trench (64, 74).
With regard to claim 15, Lin makes it clear that the device in fig. 7-14 is one memory cell in an array of memory cells in a DRAM (p. 3, paragraph 31). It is therefore understood that the substrate (60) comprises a plurality of isolation areas and a plurality of active areas between the isolation areas. The source/drain implant region (66) is in one of the active areas.
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a memory structure that comprises a word line structure having a gate structure and a dielectric cap such that the word line structure extends from a top surface of a substrate and through a source/drain implant region in the substrate with a capacitor over the source/drain implant region in combination with the suggested positioning of the capacitor relative to the gate structure and the dielectric cap as described by the applicant in claim 18.
In the examiner’s opinion, it would also not be obvious to implement a memory structure that comprises a substrate having a plurality of active areas that are between a plurality of isolation areas, with a source/drain implant region in one of the active areas, a first word line structure in a first word line trench that extends from a top surface of a substrate and through the source/drain implant in combination with the specific sidewall structure of the first word line trench and its depth relative to a second word line structure in a second word line trench which is across the isolation areas as described by the applicant in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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