DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 is rejected under 35 U.S.C. 35 U.S.C. 103 as being unpatentable over Pribble et al. (US PGPub: 2015/0002227 A1), hereinafter Pribble, in view of Pribble.
Regarding claim 1, Pribble teaches, in FIG. 7, Paragraphs [0027]-[0047], a semiconductor die comprising:
a first Group Ill nitride-based transistor (Q1) over a substrate and having a first output contact (302);
a second Group Ill nitride-based transistor (Q2) over the substrate and having a second output contact;
an output combiner inductor (L5) (D1: Fig. 5,7) over the substrate, the output combiner inductor being coupled to the first output contact (302) and to the second output contact (402) (Paragraph [0041]-[0042]); and
a radio frequency (RF) output interface (a drain terminal that serves as an output node 402 that also serves as an output combining node for the Doherty configuration) coupled to the output combiner inductor (L5) (Fig. 5,7 and Paragraphs [0041]-[0042]).
Some of the circuits like combining node showing in different Figurs which belong to different embodiments perhaps and needed explanation and clarification. These Figures are embodiments are combined to give final structure in order to meet device functionality.
Regarding claim 2, Pribble teaches the semiconductor die of claim 1, further comprising: a first RF input interface coupled to the first Group III nitride-based transistor; and a second RF input interface coupled to the second Group III nitride-based transistor (the first Group Ill nitride-based transistor and the second Group Ill nitridebased transistor are positioned in a second region of the MMIC at mid-section of die in FIG. 7);.
Regarding claim 3, Pribble teaches the semiconductor die of claim 1, further comprising: a first gate interface coupled to a gate of the first Group III nitride-based transistor; and a second gate interface coupled to a gate of the second Group III nitride-based transistor (construction of a Doherty MMIC Amplifier with two transistors and with a Wilkinson power divider input section and phase shifter)
This is also taught in ZHAO et al (US 2021/0399694 A1 discloses a semiconductor die (Paragraphs [0063]-[0068]; Fig. 3A-C, 4A-C) comprising :a first Group Ill (41 0A,B,C) (Fig. 4A-C) nitride-based transistor over a substrate; a second Group Ill (420A,B,C) (Fig. 4A-C) nitride-based transistor over the substrate; a first input matching circuit (460A,B,C) over the substrate and coupled to a gate of the first Group Ill nitride-based transistor (see also [0017]-[0023] about Doherty amplifiers with GaN transistors and Fig. 1D); and a second input matching (465A,B,C) circuit over the substrate and coupled to a gate of the second Group Ill nitride-based transistor.
Regarding claim 4, Pribble teaches the semiconductor die of claim 1, further comprising: a first drain interface for the first Group III nitride-based transistor; and a second drain interface for the second Group III nitride-based transistor (the first Group Ill nitride-based transistor and the second Group Ill nitridebased transistor are positioned in a second region of the MMIC (mid-section of die in fig. 7)).
Regarding claim 5, Pribble teaches the semiconductor die of claim 1, wherein the output combiner inductor (a drain terminal that serves as an output node 402 that also serves as an output combining node for the Doherty configuration. L5 is the inductor) is configured to implement a phase shift in an RF signal output by the first Group III nitride-based transistor.
Regarding claim 6, Pribble teaches the semiconductor die of claim 1, wherein the output combiner inductor comprises a spiral inductor (L5 I spiral inductor as shown in FIG. 5. lumped inductor L5 (implemented as a spiral inductor) as in Paragraph [0044]).
Regarding claim 7, Pribble teaches the semiconductor die of claim 1, wherein the output combiner inductor (L5) is positioned in a region of the semiconductor die between a first drain interface and a second drain interface (right of die: FIG. 7).
Regarding claim 8, Pribble teaches the semiconductor die of claim 7, wherein the RF output interface (a drain terminal that serves as an output node 402 that also serves as an output combining node for the Doherty configuration) is positioned in a region of the semiconductor die between the output combiner inductor and the second drain interface (See FIG. 5 and FIG. 7).
Regarding claim 9, Pribble teaches the semiconductor die of claim 1, wherein the output combiner inductor (L5) is positioned in a region of the semiconductor die outside of a region defined between the first Group III nitride-based transistor and the second Group III nitride-based transistor (right of die: FIG. 7).
Regarding claim 10, Pribble teaches the semiconductor die of claim 1, further comprising: a first input matching circuit over the substrate and coupled to a first gate interface of the first Group III nitride-based transistor; and a second input matching circuit over the substrate and coupled to a second gate interface of the second Group III nitride-based transistor (the first input matching circuit and the second input matching circuit are positioned in a third region of the MMIC (left of die in D1: Fig. 7).
Regarding claim 11, Pribble teaches the semiconductor die of claim 10, further comprising: a first RF input interface (Gate is the input. TL4 in FIG. 3. a drain terminal that serves as an output node 402 that also serves as an output combining node for the Doherty configuration) coupled to the first input matching circuit; and a second RF input interface coupled to the second input matching circuit.
Regarding claim 12, Pribble teaches the semiconductor die of claim 11, further comprising a phase shifter inductor (L3) over the substrate and positioned in a region of the semiconductor die between the second RF input interface and the second input matching circuit.
Regarding claim 13, Pribble teaches the semiconductor die of claim 12, wherein the first input matching circuit and the second input matching circuit are coupled to a common RF input interface of the semiconductor die (FIG. 4 where first and second RF input matching circuit are shown).
Regarding claim 14, Pribble teaches the semiconductor die of claim 13, further comprising an input combiner inductor (L5) over the substrate and positioned in a region of the semiconductor die between the common RF input interface and the second input matching circuit (FIG. 7).
Regarding claim 15, Pribble teaches the semiconductor die of claim 10, further comprising a blocking capacitor (C8) over the substrate and coupled to the second input matching circuit (the peaking amplifier 130' includes a GaN transistor Q2 having a source terminal coupled to a ground node and a drain terminal that serves as an output node 402 that also serves as an output combining node for the Doherty configuration. Matching circuitry including resistors R5, R6, a lumped inductor L4, capacitors C6, C7, C8, and transmission line segments TL5, TL6, TL7, TL8, TL9, TL10 couple a gate terminal of the transistor Q2 to an input node 203 and biasing nodes 403, 404).
Regarding claim 16, Pribble teaches the semiconductor die of claim 10, wherein: the output combiner inductor is positioned in a first region of the semiconductor die, the first Group III nitride-based transistor (Q1) and the second Group III nitride-based transistor (Q2) are positioned in a second region (mid-section of die in fig. 7) of the semiconductor die, and the first input matching circuit and the second input matching circuit are positioned in a third region of the semiconductor die (left of die in D1: Fig. 7); and the second region of the semiconductor die is positioned between the first region of the semiconductor die and the third region of the semiconductor die (see FIG. 7, mid-section would be between left and right section).
Regarding claim 17, Pribble teaches the semiconductor die of claim 1, wherein the first Group III nitride-based transistor comprises a first plurality of transistor unit cells (see FIG. 7) and the second Group III nitride-based transistor comprises a second plurality of transistor cells (FIG. 7, Paragraph [0044]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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