DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 and 21-26 in the reply filed on 6/29/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (US pub 20210098588).
With respect to claim 10, Chung et al. teach a method, comprising (see figs. 1-22C, particularly figs. 11A-C, 17A-C, 18A-C, and 20A-20B and associated text):
forming a plurality of semiconductor nanostructures 210A,210B vertically stacked above a substrate 202;
forming a dielectric structure 212 suspended above a topmost one of the semiconductor nanostructures;
forming a plurality of inner spacers 230 interleaving the semiconductor nanostructures;
forming an epitaxial feature 240 abutting the semiconductor nanostructures; and
forming a gate structure 268 wrapping around each of the semiconductor nanostructures and the dielectric structure.
With respect to claim 11, Chung et al. teach planarizing the gate structure to expose the dielectric structure (see figs. 18A-C); depositing an interlayer dielectric layer 272, 274 over the dielectric structure; and forming a gate plug 278 extending through the interlayer dielectric layer and the dielectric structure. See figs. 1-22C, particularly figs. 11A-C, 17A-C, 18A-C, and 20A-20B and associated text.
With respect to claim 12, Chung et al. teach the gate structure includes an interfacial layer 262, a high-k dielectric layer 264, and a gate electrode layer 266, the interfacial layer is in contact with the semiconductor nanostructures, and the high-k dielectric layer is in contact with the dielectric structure. See figs. 1-22C, particularly figs. 11A-C, 17A-C, 18A-C, and 20A-20B and associated text.
With respect to claim 13, Chung et al. teach depositing a dielectric layer 252 on a top surface of the epitaxial feature, wherein the gate structure is in contact with the dielectric layer. See figs. 1-22C, particularly figs. 11A-C, 17A-C, 18A-C, and 20A-20B and associated text.
Allowable Subject Matter
Claims 1-9 and 21-26 are allowed.
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related process of forming a semiconductor structure having a semiconductor stack, a dielectric layer suspended over the stack, having inner space between parts of the stack, having an epitaxial feature in contact with stack, having a gate structure around the stack and dielectric layer as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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