DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 and 6-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 7-9, 11-16 and 18-20 of U.S. Patent No. 12,068,260 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 1, 12,068,269 B2 (claims 1, 11 and 19) disclose a semiconductor die package, comprising: a package substrate having a first surface; a semiconductor device disposed over the first surface of the package substrate; a ring structure disposed over the first surface of the package substrate and laterally surrounding the semiconductor device, wherein the ring structure comprises: a lower ring portion arranged around a periphery of the package substrate, wherein a plurality of notches are formed along an outer periphery of the lower ring portion, wherein each of the plurality of notches extends from the outer periphery toward an inner periphery of the lower ring portion but does not reach the inner periphery; and an upper ring portion formed on the lower ring portion, wherein the upper ring portion laterally extends toward the semiconductor device, so that an inner periphery of the upper ring portion is closer to the semiconductor device than an inner periphery of the lower ring portion; and an adhesive layer interposed between a bottom surface of the lower ring portion and the first surface of the package substrate.
In regards to claim 2, 12,068,269 B2 (claim 2) disclose wherein an outer periphery of the upper ring portion is spaced apart from the outer periphery of the lower ring portion.
In regards to claim 3, 12,068,269 B2 (claims 3, 13) disclose wherein there is a gap between a bottom surface of the upper ring portion and the first surface of the package substrate.
In regards to claim 6, 12,068,269 B2 (claim 6) disclose wherein the lower ring portion has a rectangular ring shape with four corners and four sides, and the plurality of notches are formed on some or all of the four sides.
In regards to claim 7, 12,068,269 B2 (claim 7) disclose wherein each of the plurality of notches extends in a direction perpendicular to an extending direction of the respective side of the lower ring portion.
In regards to claim 8, 12,068,269 B2 (claim 18) disclose, wherein some of the plurality of notches extends in a direction oblique to an extending direction of the respective side of the lower ring portion.
In regards to claim 9, 12,068,269 B2 (claim 8) disclose wherein the plurality of notches have a uniform size.
In regards to claim 10, 12,068,269 B2 (claim 9) disclose wherein the plurality of notches have two or more different sizes.
In regards to claim 11, 12,068,269 B2 (claims 1, 11 and 19) disclose A semiconductor die package, comprising: a package substrate having a first surface; a semiconductor device disposed over the first surface of the package substrate; a ring structure disposed over the first surface of the package substrate and laterally surrounding the semiconductor device, wherein the ring structure comprises: a lower ring portion having a rectangular ring shape, wherein at least some sides of the lower ring portion respectively have one or more a plurality of notches that penetrate a top surface and a bottom surface of the lower ring portion; and an upper ring portion, which has a rectangular ring shape, formed on the lower ring portion, wherein the upper ring portion has a part laterally extending toward the semiconductor device and beyond an inner periphery of the lower ring portion; and an adhesive layer interposed between the bottom surface of the lower ring portion and the first surface of the package substrate.
In regards to claim 12, 12,068,269 B2 (claim 12) disclose wherein a part of the top surface of the lower ring portion is exposed from the upper ring portion.
In regards to claim 13, 12,068,269 B2 (claim 13) disclose wherein a bottom surface of the part of the upper ring portion is spaced apart from the first surface of the package substrate, and is separated from the adhesive layer.
In regards to claim 14, 12,068,269 B2 (claims 14 and 20) disclose wherein the lower ring portion comprises four corners and four sides, and the sides of the lower ring portion, which have the notches, respectively further have a plurality of solid columns, wherein each of the notches is interposed between adjacent solid columns or between adjacent solid column and corner, and the notches extend from an outer periphery of the lower ring portion toward the inner periphery of the lower ring portion.
In regards to claim 15, 12,068,269 B2 (claim 15) disclose wherein the adhesive layer is only formed at the four corners of the lower ring portion.
In regards to claim 16, 12,068,269 B2 (claim 16) disclose wherein the adhesive layer is formed at the four corners and the plurality of solid columns of the lower ring portion.
Allowable Subject Matter
Claims 17-20 are allowed.
None of the prior art of record discloses “bonding a semiconductor device to a package substrate; disposing a ring structure over the package substrate to surround the semiconductor device, wherein the ring structure comprises: a lower ring portion arranged around a periphery of the package substrate, wherein a plurality of notches are formed along an outer periphery of the lower ring portion… and attaching the ring structure to the package substrate through an adhesive layer between the lower ring portion and the package substrate”.
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 August 11, 2026
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