DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6, 9, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2016/0233227).
Regarding claim 1, Zhang teaches (FIG. 4, 5):
A 3D DRAM semiconductor processing method comprising:
depositing a plurality of layers (32/142) of amorphous or poly-crystalline material over a substrate, to form a film stack;
depositing a metal seed layer (160) adjacent and parallel to an outer surface of the plurality of layers;
annealing the film stack, driving the metal seed layer in a direction generally perpendicular to the plurality of layers of amorphous or poly-crystalline material ([0065] – [0067]); and
removing a remaining portion of the metal seed layer ([0068]).
Regarding claim 2, Zhang teaches:
The method of claim 1, wherein the film stack comprises alternating layers of a channel material and a sacrificial material ([0047]).
Regarding claim 3, Zhang teaches ([0048] – [0053]):
The method of claim 1, wherein the film stack comprises one or more layers of doped or undoped silicon, carbon, or combinations thereof.
Regarding claim 4, Zhang teaches ([0048] – [0053]):
The method of claim 3, wherein the film stack comprises one or more layers of a dielectric material.
Regarding claim 5, Zhang teaches ([0048] – [0053]):
The method of claim 4, wherein the dielectric material comprises silicon oxide, silicon nitride, doped or undoped silicon germanium, or a combination thereof.
Regarding claim 6, Zhang teaches:
The method of claim 1, further comprising depositing a capping layer (70) over a top surface of the film stack.
Regarding claim 9, Zhang teaches (FIG. 4):
The method of claim 1, wherein the metal seed layer is deposited over a last layer of the plurality of layers of amorphous or poly-crystalline material.
Regarding claim 15, Zhang teaches ([0065]):
The method of claim 1, wherein the metal seed layer is deposited at a thickness of about 1 Å to about 100 Å.
Regarding claim 16, Zhang teaches (FIG. 4, 5):
A 3D DRAM semiconductor processing method comprising:
depositing a plurality of layers of amorphous or poly-crystalline material over a substrate, to form a film stack (32/142);
depositing a metal seed layer (160) over the film stack;
depositing a capping layer (70) over the metal seed layer;
annealing the film stack, to drive the metal seed layer in a direction generally perpendicular to the plurality of layers of amorphous or poly-crystalline material ([0065] – [0067]); and
removing a remaining portion of the metal seed layer overlying the metal seed layer ([0068]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) as applied to claim 1 above, and further in view of Zhang2 (US 2024/0170424).
Regarding claim 7, Zhang fails to expressly disclose:
The method of claim 1, wherein the metal seed layer is deposited between the substrate and a first layer of the plurality of layers of amorphous or poly-crystalline material.
However, Zhang2 teaches a method of forming a layered memory stack on a temporary multilayer substrate (FIG. 9A – 9G).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the temporary substrate process of Zhang2 to include the metal induced crystallization process of Zhang for the predictable advantage of improving device performance in a well-known and conventional manner.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) in view of Zhang2 et al. (US 2024/0170424) as applied to claim 7 above, and further in view of Sharangpani et al. (US 2024/0170424).
Regarding claim 8, Zhang (FIG. 4, 5) and Zhang2 (FIG. 9A) teach capping layers, but fail to expressly disclose the capping layers include a gettering layer:
The method of claim 7, further comprising a capping layer disposed over a last layer of the plurality of layers of amorphous or poly-crystalline material, wherein the capping layer comprises a gettering layer.
However, Sharangpani teaches a method of forming a 3D memory device which includes a temporary gettering layer for capturing stray metal atoms (FIG. 15G, [0131] – [0133]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the gettering layer of Sharangpani in the device of Zhang for the predictable advantage of removing leftover metal atoms from the active structure of the device to reduce device defectivity in a well-known and conventional manner.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) as applied to claim 9 above, and further in view of Sharangpani et al. (US 2024/0170424).
Regarding claim 10, Zhang fails to expressly disclose:
The method of claim 9, wherein the substrate comprises a gettering layer.
However, Sharangpani teaches a method of forming a 3D memory device which includes a temporary gettering layer for capturing stray metal atoms (FIG. 15G, [0131] – [0133]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the gettering layer of Sharangpani in the device of Zhang for the predictable advantage of removing leftover metal atoms from the active structure of the device to reduce device defectivity in a well-known and conventional manner.
Claims 11 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) as applied to claim 1 above, and further in view of Zhang2 (US 2024/0170424).
Regarding claim 11, Zhang fails to expressly disclose:
The method of claim 1, further comprising removing the substrate and any seed metal contained in or adjacent to the substrate after annealing, exposing a lower surface of the film stack.
However, Zhang2 teaches a method of forming a layered memory stack on a temporary multilayer substrate (FIG. 9A – 9G).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the temporary substrate process of Zhang2 to include the metal induced crystallization process of Zhang for the predictable advantage of improving device performance in a well-known and conventional manner.
Regarding claim 12, Zhang2 teaches (FIG. 10A – 13B):
The method of claim 11, further comprising bonding a peripheral component to the lower surface.
Regarding claim 13, Zhang2 teaches (FIG. 9A – 9G):
The method of claim 11, further comprising flipping an orientation of the film stack, wherein the lower surface is disposed above an upper surface, prior to removing the substrate.
Regarding claim 14, Zhang2 teaches (FIG. 9A – 9G):
The method of claim 13, further comprising bonding a secondary substrate to an upper surface of the film stack prior to flipping the orientation of the film stack.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) as applied to claim 16 above, and further in view of Zhang2 (US 2024/0170424).
Regarding claim 17, Zhang fails to expressly disclose:
The semiconductor processing method of claim 16, further comprising removing the substrate and any seed metal contained in or adjacent to the substrate after annealing, exposing a lower surface of the film stack.
However, Zhang2 teaches a method of forming a layered memory stack on a temporary multilayer substrate (FIG. 9A – 9G).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the temporary substrate process of Zhang2 to include the metal induced crystallization process of Zhang for the predictable advantage of improving device performance in a well-known and conventional manner.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) in view of Zhang2 et al. (US 2024/0170424) as applied to claim 16 above, and further in view of Sharangpani et al. (US 2024/0170424).
Regarding claim 18, Zhang fails to expressly disclose:
The semiconductor processing method of claim 16, wherein at least one of the capping layer and the substrate comprise a gettering layer.
However, Sharangpani teaches a method of forming a 3D memory device which includes a temporary gettering layer for capturing stray metal atoms (FIG. 15G, [0131] – [0133]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the gettering layer of Sharangpani in the device of Zhang for the predictable advantage of removing leftover metal atoms from the active structure of the device to reduce device defectivity in a well-known and conventional manner.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang2 (US 2024/0170424) in view of Zhang et al. (US 2016/0233227).
Regarding claim 19, Zhang2 teaches (FIG. 9A – 9G):
A method of forming a three-dimensional dynamic random-access memory (3D DRAM) device, comprising:
providing a substrate (910) to a processing region of a semiconductor processing chamber;
depositing a plurality of alternating pairs of an amorphous or poly-crystalline silicon-containing material and a silicon-and-germanium-containing material layer over the metal seed layer, to form a film stack (942/944);
annealing the film stack ([0137]), to form a seed metal layer over the plurality of alternating pairs of the amorphous or poly-crystalline silicon-containing material; and
removing the seed metal layer (FIG. 9F).
Zhang2 teaches a multilayer temporary substrate 910, and thermal anneal processes to modify and activate material layers, but fails to expressly disclose a metal seed layer.
However, Zhang teaches a method of forming a layered memory stack including performing a modifying anneal with a metal layer to induce crystallization.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the metal induced crystallization of Zhang in the temporary substrate process of Zhang2 for the predictable advantage of improving device performance in a well-known and conventional manner.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2016/0233227) in view of Zhang2 et al. (US 2024/0170424) as applied to claim 19 above, and further in view of Sharangpani et al. (US 2024/0170424).
Regarding claim 20, Zhang (FIG. 4, 5) and Zhang2 (FIG. 9A) teach capping layers, but fail to expressly disclose the capping layers include a gettering layer:
The method of claim 19, further comprising depositing a capping layer over the plurality of alternating pairs of the amorphous or poly-crystalline silicon-containing material, wherein the capping layer comprises a gettering layer.
However, Sharangpani teaches a method of forming a 3D memory device which includes a temporary gettering layer for capturing stray metal atoms (FIG. 15G, [0131] – [0133]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the gettering layer of Sharangpani in the device of Zhang for the predictable advantage of removing leftover metal atoms from the active structure of the device to reduce device defectivity in a well-known and conventional manner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
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