Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on October 22, 2024 and December 17, 2025 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 5 recites “ … the bottom conductive
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connecting portion is not in contact with the first protection layer and the second protection layer”. However, all the Figures show the bottom conductive connecting portion is actually in contact with the first protection layer and the second protection layer. For example, Fig. 15B shows the bottom conductive connecting portion 552 is in contact with both the first protection layer 538 and the second protection layer 548 (Par. 0105-0106).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 was rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 5 recites “ … the bottom conductive connecting portion is not in contact with the first protection layer and the second protection layer”. However, all the Figures show the bottom conductive connecting portion is actually in contact with the first protection layer and the second protection layer. For example, Fig. 15B shows the bottom conductive connecting portion 552 is in contact with both the first protection layer 538 and the second protection layer 548 (Par. 0105-0106). Appropriate correction/clarification is requested.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 was rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 5 recites “ … the bottom conductive connecting portion is not in contact with the first protection layer and the second protection layer”. However, all the Figures show the bottom conductive connecting portion is actually in contact with the first protection layer and the second protection layer. For example, Fig. 15B shows the bottom conductive connecting portion 552 is in contact with both the first protection layer 538 and the second protection layer 548 (Par. 0105-0106). Appropriate correction/clarification is requested.
Allowable Subject Matter
Claims 1-4 and 6 are allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 1: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a method for manufacturing a semiconductor device, comprising: providing a carrier structure, comprising: providing a carrier substrate; forming a bonding layer on the carrier substrate; and forming a heat dissipation unit in the carrier substrate and the bonding layer, wherein the carrier substrate, the bonding layer, and the heat dissipation unit together configure the carrier structure; providing a first die structure having a through semiconductor via; forming an intervening bonding layer on the first die structure; bonding the first die structure onto the carrier structure through the intervening bonding layer; and bonding a second die structure onto the first die structure, wherein the second die structure and the first die structure are electrically coupled by the through semiconductor via, wherein forming the heat dissipation unit in the carrier substrate and the bonding layer comprises: forming a conductive plate; and forming a composite via on the conductive plate, wherein the composite via comprises a first through via, a second through via, and a bottom conductive connecting portion, wherein a bottom portion of the first through via and a bottom portion of the second through via are covered by the bottom conductive connecting portion.
The most relevant prior art reference due to Chen et al. (Pub. No.: US 2018/0366437 A1) substantially discloses a method for manufacturing a semiconductor device, comprising: providing a carrier structure, comprising: providing a carrier substrate (Par. 0037; Fig. 7 - carrier substrate comprising layers 54B, 52B, 50B, 54A, 52A and 50A); forming a bonding layer on the carrier substrate (Par. 0028; Fig. 7 - bonding layer 40); and forming a heat dissipation unit in the carrier substrate and the bonding layer, wherein the carrier substrate, the bonding layer, and the heat dissipation unit together configure the carrier structure (Par. 0035; Fig. 7 – under BRI, heat dissipation unit comprising 56A and 56B);
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providing a first die structure having a Par. 0019; Fig. 7 – first die 20A); forming an intervening bonding layer on the first die structure (Par. 0021; Fig. 7 – intervening bonding layer comprising metal pads 32A); bonding the first die structure onto the carrier structure through the intervening bonding layer (Fig. 7); and Par. 0038; Fig. 7 –conductive plate comprising 56B); and forming a composite via on the conductive plate, wherein the composite via comprises a first through via, a second through via, and a bottom conductive connecting portion (Par. 0032-0038; Fig. 7 –composite vias are formed of vias underneath conductive plate comprising 56B; bottom conductive connecting portions comprising element 44); wherein a bottom portion of the first through via and a bottom portion of the second through via are covered by the bottom conductive connecting portion (Par. 0032- 0038; Fig. 7 –composite vias are formed of vias underneath conductive plate comprising 56B; bottom conductive connecting portions comprising element 44).
This prior art, however, does not disclose a method for manufacturing a semiconductor device, comprising: bonding a second die structure onto the first die structure, wherein the second die structure and the first die structure are electrically coupled by the through semiconductor via, wherein forming the heat dissipation unit in the carrier substrate and the bonding layer comprises: forming a conductive plate; and forming a composite via on the conductive plate, wherein the composite via comprises a first through via, a second through via, and a bottom conductive connecting portion, wherein a bottom portion of the first through via and a bottom portion of the second through via are covered by the bottom conductive connecting portion.
Additionally, Yu et al. (Patent No.: US 10,163,750 A) teaches a method for manufacturing a semiconductor device, comprising: providing a carrier structure, comprising: providing a carrier substrate (Par. 0094; Figs. 28-29 - carrier substrate comprising carrier 605);
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forming a bonding layer on the carrier substrate (Par. 0094-0097; Figs. 28-30 - bonding layer comprising release layer 610 and processed wafer 511 (under BRI)); and forming a heat dissipation unit in the carrier substrate and the bonding layer, wherein the carrier substrate, the bonding layer, and the heat dissipation unit together configure the carrier structure (Par. 0089-0097; Figs. 28-30 – under BRI, heat dissipation unit comprising vias 525, 535, 546); providing a first die structure having a through semiconductor via (Par. 0097-0107; Figs. 28-33 - first die 613/619/615); forming an intervening bonding layer on the first die structure (Par. 0102-0107; Figs. 28-33 - although this prior art mainly stresses on direct bonding or hybrid bonding, it states other possibilities including having an intervening bonding layer); bonding the first die structure onto the carrier structure through the intervening bonding layer ((Par. 0102-0107; Figs. 28-33);and bonding a second die structure onto the first die structure, wherein the second die structure and the first die structure are electrically coupled by the through semiconductor via (Par. 0102-0107; Figs. 28-36 – second die 622/624/628), wherein forming the heat dissipation unit in the carrier substrate and the bonding layer comprises: Par. 0089-0097; Figs. 28-30);
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 1 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 1 is deemed patentable over the prior arts.
Regarding Claims 2-4 & 6: these claims are allowed because of their dependency status from claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (Pub. No; 2014/0054761 A1) – This prior art is a relevant prior art teaching carrier structure with heat dissipation unit, die stacks on the carrier structure and composite vias (Fig. 2a)
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07/23/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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