DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 5-6, 10, and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the in-recess spacer has a square ring-shaped cross-sectional profile from a top-view perspective”, as recited in claim 5.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the buried conductive layer has a square cross-sectional profile from a top-view perspective”, as recited in claim 6.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein a top surface of the air gap structure is coplanar with a top surface of the buried conductive layer”, as recited in claim 10.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the in-recess spacer has a square ring-shaped cross-sectional profile from a top-view perspective”, as recited in claim 12.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the buried conductive layer has a square cross-sectional profile from a top-view perspective”, as recited in claim 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song).
Regarding Claim 11: Song discloses a semiconductor device (see Song, Fig.3 as shown below and ¶ [0002]), comprising:
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a substrate a buried conductive layer (115) (see Song, Fig.3 as shown above) comprising:
a bottom portion positioned in the substrate (see Song, Fig.3 as shown above); and
a top portion positioned in the substrate and on the bottom portion (see Song, Fig.3 as shown above);
a shallow trench isolation (STI) structure (102) positioned in the substrate (see Song, Fig.3 as shown above); and
an in-recess spacer (116) positioned in the substrate, surrounding the bottom portion, and covered by the top portion (see Song, Fig.3 as shown above);
wherein a top surface of the top portion and a top surface of the substrate are substantially coplanar (see Song, Fig.3 as shown above);
wherein a bottom surface of the in-recess spacer (116) and a bottom surface of the bottom portion are substantially coplanar (see Song, Fig.3 as shown above);
wherein a sidewall of the in-recess spacer (116) and a sidewall of the top portion are substantially coplanar (see Song, Fig.3 as shown above).
Regarding Claim 14: Song discloses a semiconductor device as set forth in claim 11 as above. Song further teaches wherein the buried conductive layer (115) comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof (note: “metallic layer is a conductive layer including metal, and the metallic layer can include a metal layer, a metal oxide layer, a metal nitride layer and so on”) (see Song, Fig.3 as shown above, ¶ [0041], and ¶ [0045]- ¶ [0046]).
Regarding Claim 15: Song discloses a semiconductor device as set forth in claim 14 as above. Song further teaches wherein the in-recess spacer (116/ Fig.4B, 40) comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride (see Song, Fig.3 as shown above,, Fig.4B, and ¶ [0057]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) in view of Wei et al. (U.S. 2022/0216210 A1, hereinafter refer to Wei).
Regarding Claim 1: Song discloses a semiconductor device (see Song, Fig.3 as shown above and ¶ [0002]), comprising:
a substrate (see Song, Fig.3 as shown above);
a buried conductive layer (115) (see Song, Fig.3 as shown above) comprising:
a bottom portion positioned in the substrate (see Song, Fig.3 as shown above); and
a top portion positioned in the substrate and on the bottom portion (see Song, Fig.3 as shown above);
an isolation layer (102) positioned in the substrate (see Song, Fig.3 as shown above);
an in-recess spacer (116) positioned in the substrate, surrounding the bottom portion, and covered by the top portion (see Song, Fig.3 as shown above);
wherein a top surface of the top portion and a top surface of the substrate are substantially coplanar (see Song, Fig.3 as shown above);
wherein a bottom surface of the in-recess spacer (116) and a bottom surface of the bottom portion are substantially coplanar (see Song, Fig.3 as shown above);
wherein a sidewall of the in-recess spacer (116) and a sidewall of the top portion are substantially coplanar (see Song, Fig.3 as shown above).
Song is silent upon explicitly disclosing wherein an air gap structure positioned in the isolation layer.
For support see Wei, which teaches wherein an air gap structure (117a) positioned in the isolation layer (104) (see Wei, Fig.9B as shown below and ¶ [0005]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song and Wei to enable air gap structure of in the isolation layer of Song as taught by Wei in order to reduce the parasitic capacitance between the bit line and the adjacent capacitive contact structure.
Regarding Claim 2: Song as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei further teaches wherein a width ratio (CD2/CD1) of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion is between about 0.5 and about 0.95 (greater than zero) (note: the term “about" was found indefinite because the range of specific activity is not covered by the term “about”) (see Song, Fig.3 as shown above and ¶ [0060]).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion through routine experimentation and optimization to obtain optimal or desired contact resistance because the width ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 3: Song as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei is silent upon explicitly disclosing wherein a ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion is between about 0.025 and about 0.25.
However, the combination of Song and Wei teaches wherein a ratio of a thickness of the in-recess spacer (116) to a width of the top surface of the top portion is between about 1.0 (note: the term “about" was found indefinite because the range of specific activity is not covered by the term “about”) (see Song, Fig.3 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion through routine experimentation and optimization to obtain optimal or desired parasitic capacitance between adjacent buried conductive layer because the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the configuration of the in-recess spacer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed in-recess spacer was significant.
Regarding Claim 4: Song as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei is silent upon explicitly disclosing wherein a ratio of a height of the in-recess spacer to a height of the buried conductive layer is between about 0.5 and about 0.85.
However, the combination of Song and Wei teaches wherein a ratio of a height of the in-recess spacer (116) to a height of the buried conductive layer (115) is between about 0.5 and about 0.85 (greater than zero) (note: the term “about" was found indefinite because the range of specific activity is not covered by the term “about”) (see Song, Fig.3 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the height of the in-recess spacer to a height of the buried conductive layer through routine experimentation and optimization to obtain optimal or desired contact resistance because the height of the in-recess spacer to a height of the buried conductive layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 7: Song as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei further teaches wherein the buried conductive layer (115) comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof (note: “metallic layer is a conductive layer including metal, and the metallic layer can include a metal layer, a metal oxide layer, a metal nitride layer and so on”) (see Song, Fig.3 as shown above, ¶ [0041], and ¶ [0045]- ¶ [0046]).
Regarding Claim 8: Song as modified teaches a semiconductor device as set forth in claim 7 as above. The combination of Song and Wei further teaches wherein the in-recess spacer (116/ Fig.4B, 40) comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride (see Song, Fig.3 as shown above,, Fig.4B, and ¶ [0057]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) and Wei et al. (U.S. 2022/0216210 A1, hereinafter refer to Wei) as applied to claim 1 above, and further in view of Singh et al. (U.S. 2019/0385892 A1, hereinafter refer to Singh).
Regarding Claim 9: Song as modified teaches a semiconductor device as applied to claim 1 above. The combination of Song and Wei is silent upon explicitly disclosing wherein the air gap structure includes an air gap enclosed by a liner.
For support see Singh, which teaches wherein the air gap structure(130) includes an air gap (130) enclosed by a liner (310) (see Singh, Fig.21 and ¶ [0013]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song, Wei, and Singh to enable the combination of Song’s and Wei’s air gap structure includes an air gap enclosed by a liner as taught by Singh in order to improve isolation properties between devices.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song).
Regarding Claim 20: Song discloses a semiconductor device as set forth in claim 11 as above. Song further teaches wherein a ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion is between about 0.5 and about 0.95 (greater than zero) (note: the term “about" was found indefinite because the range of specific activity is not covered by the term “about”) (see Song, Fig.3 as shown above and ¶ [0060]).
Song is silent upon explicitly disclosing wherein a ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion is between about 0.025 and about 0.25; and a ratio of a height of the in-recess spacer to a height of the buried conductive layer is between about 0.5 and about 0.85.
However, the combination of Song and Wei teaches wherein a ratio of a thickness of the in-recess spacer (116) to a width of the top surface of the top portion is between about 1.0 (note: the term “about" was found indefinite because the range of specific activity is not covered by the term “about”) (see Song, Fig.3 as shown above);
wherein a ratio of a height of the in-recess spacer (116) to a height of the buried conductive layer (115) is between about 0.5 and about 0.85 (greater than zero) (note: the term “about" was found indefinite because the range of specific activity is not covered by the term “about”) (see Song, Fig.3 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; and the height of the in-recess spacer to a height of the buried conductive layer through routine experimentation and optimization to obtain optimal or desired parasitic capacitance between adjacent buried conductive layer because the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; and the height of the in-recess spacer to a height of the buried conductive layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Note: the configuration of the in-recess spacer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed in-recess spacer was significant.
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) as applied to claim 11 above, and further in view of Kim et al. (U.S. 2012/0231605 A1, hereinafter refer to Kim).
Regarding Claim 16: Song discloses a semiconductor device as applied to claim 11 above. Song is silent upon explicitly disclosing wherein the STI structure includes a first liner, a second liner disposed over the first liner, a third liner disposed over the second liner, and a trench-filling layer disposed over the third liner.
For support see Kim, which teaches wherein the STI structure (130) includes a first liner (110a), a second liner (110b) disposed over the first liner (110a), a third liner (110c) disposed over the second liner (110c), and a trench-filling layer (112) disposed over the third liner (110c) (see Kim, Fig.5B as shown below and ¶ [0090]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song and Kim to enable the Song’s STI structure to includes a first liner, a second liner disposed over the first liner, a third liner disposed over the second liner, and a trench-filling layer disposed over the third liner as taught by Kim in order to reduce power consumption and improve data storage capability.
Regarding Claim 17: Song as modified teaches a semiconductor device as set forth in claim 16 as above. The combination of Song and Kim further teaches wherein the trench filling layer (112) is surrounded by the third liner (110c), the third liner (110c) is surrounded by the second liner (110b), and the second liner (110b) is separated from the substrate (100) by the first liner (110a), and a top surface of the first liner (110a), a top surface of the second liner (110b), a top surface of the third liner (110c) and a top surface of the trench filling layer (112) are substantially coplanar (see Kim, Fig.5B as shown above).
Claim(s) 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) and Kim et al. (U.S. 2012/0231605 A1, hereinafter refer to Kim) as applied to claim 17 above, and further in view of Fan (U.S. 2023/0369488 A1, hereinafter refer to Fan).
Regarding Claim 18: Song as modified teaches a semiconductor device as applied to claim 17 above. The combination of Song and Kim further teaches wherein the first liner (110c), the second liner (110b) and the third liner (110c) of the STI structure (120) are made of different materials, and the first liner is made of silicon oxide, the second liner is made of nitride (see Kim, Fig.5B as shown above and ¶ [0053]).
The combination of Song and Kim is silent upon explicitly disclosing wherein the third liner is made of silicon oxynitride.
For support see Fan, which teaches wherein the third liner (393) is made of silicon oxynitride (see Fan, Fig.15 and ¶ [0061]- ¶ [0064]).
The combination of Song and Kim teaches the claimed invention except for the material of the third liner. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song, Kim, and Fan to enable the known the third liner material as taught by Fan for forming the third liner layers of the combination of Song and Kim, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Regarding Claim 19: Song as modified teaches a semiconductor device as set forth in claim 18 as above. The combination of Song, Kim, and Fan further teaches wherein a first etching selectivity exists between the second liner and the trench-filling layer, and a second etching selectivity exists between the third liner and the trench-filling layer (see Kim, Fig.5B as shown above or see Fan, Fig.15).
Note: the patentability of a product does not depend on its method of production.
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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