DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 -4, 7, and 17-19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being antcipated by RYU et al. (U.S. 2024/0055425 A1, hereinafter refer to RYU).
Regarding Claim 1: RYU discloses a semiconductor device structure (see RYU Figs.13-14 as shown below and ¶ [0002]), comprising:
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a first source/drain region (120) (note: the source/drain regions 120 may be disposed on the active pattern 115 and positioned on both (opposing) sides of the gate lines (e.g., GL1, GL2, and GL3)) (see RYU Figs.13-14 as shown above and ¶ [0044]);
a second source/drain region (120) disposed adjacent the first source/drain region (120) along a first direction (note: the source/drain regions 120 may be disposed on the active pattern 115 and positioned on both (opposing) sides of the gate lines (e.g., GL1, GL2, and GL3)) (see RYU Figs.13-14 as shown above and ¶ [0044]);
a third source/drain region (120) disposed adjacent the first source/drain region (120) along a second direction substantially perpendicular to the first direction (note: the source/drain regions 120 may be disposed on the active pattern 115 and positioned on both (opposing) sides of the gate lines (e.g., GL1, GL2, and GL3)) (see RYU Figs.13-14 as shown above and ¶ [0044]);
a first gate electrode layer (165 of GL1) disposed between the first source/drain region (120) and the third source/drain region (120) (see RYU Figs.13-14 as shown above);
a second gate electrode layer (165 of GL2) disposed adjacent the second source/drain region (120) (see RYU Figs.13-14 as shown above); and
a first dielectric material (170) disposed between the first and second gate electrode layers (165 of GL1/GL2), wherein the first dielectric material (170) has a length less than or equal to a first distance between the first and second source/drain regions (120) (see RYU Figs.13-14 as shown above).
Regarding Claim 2: RYU discloses a semiconductor device structure as set forth in claim 1 as above. RYU further teaches wherein first and second gate spacers, wherein the first and second gate electrode layers (165 of GL1/GL2) are disposed between the first and second gate spacers (164 of GL1/GL2) (see RYU Figs.13-14 as shown above).
Regarding Claim 3: RYU discloses a semiconductor device structure as set forth in claim 2 as above. RYU further teaches wherein the first and second gate spacers (164 of GL1/GL2) are disposed between the first and third source/drain regions (120) (see RYU Figs.13-14 as shown above).
Regarding Claim 4: RYU discloses a semiconductor device structure as set forth in claim 2 as above. RYU further teaches wherein the first dielectric material (170) is disposed between the first and second gate spacers (164 of GL1/GL2) (see RYU Figs.13-14 as shown above).
Regarding Claim 7: RYU discloses a semiconductor device structure as set forth in claim 1 as above. RYU further teaches wherein the first dielectric material (170) has a width less than or equal to a second distance between the first and third source/drain regions (120) (see RYU Figs.13-14 as shown above)..
Regarding Claim 17: RYU discloses a method for forming a semiconductor device structure (see RYU Figs.12-14 as shown above and ¶ [0002]), comprising:
forming first and second gate spacers (164/166) over a substrate (101) (see RYU Fig.12 as shown above);
forming first and second source/drain regions (120) over the substrate (101), wherein the first and second source/drain regions (120) are aligned along a first direction and adjacent the first gate spacer (164/166) (see RYU Fig.12 as shown above);
forming a gate electrode layer (165) between the first and second gate spacers (164/166) (see RYU Fig.12 as shown above);
forming an opening (CT) in the gate electrode layer (165), wherein the opening (CT) has a dimension along the first direction that is less than or equal to a distance between the first and second source/drain regions (120) (see RYU Figs.12-14 as shown above and ¶ [0079]- ¶ [0081]); and
depositing a dielectric material (170) in the opening (CT) (see RYU Figs.12-14 as shown above and ¶ [0079]- ¶ [0081]).
Regarding Claim 18: RYU discloses a method for forming a semiconductor device structure as set forth in claim 17 as above. RYU further teaches wherein the opening (CT) is formed between the first and second gate spacers (164/166 of GL1/GL2) (see RYU Figs.12-14 as shown above).
Regarding Claim 19: RYU discloses a method for forming a semiconductor device structure as set forth in claim 17 as above. RYU further teaches wherein the opening (CT) extends into the first and second gate spacers (164/166 of GL1/GL2) (see RYU Figs.12-14 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (U.S. 2024/0055425 A1, hereinafter refer to RYU) as applied to claim 1 above, and further in view of Liaw (U.S. 2021/0202498 A1, hereinafter refer to Liaw).
Regarding Claim 5: RYU discloses a semiconductor device structure as applied to claim 1 above. RYU is silent upon explicitly disclosing wherein a second dielectric material disposed adjacent the third source/drain region, wherein the second dielectric material extends across first and second fin structures.
For support see Liaw, which teaches wherein a second dielectric material (240A) disposed adjacent the third source/drain region (214), wherein the second dielectric material (240A) extends across first and second fin structures (206/208) (see Liaw, Figs.8 and 11 as shown below and ¶ [0020]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of RYU and Liaw to enable the second dielectric material to be disposed adjacent the third source/drain region, wherein the second dielectric material extends across first and second fin structures as taught by Liaw allowing better gate control, lowered leakage current, and improved scaling capability for various IC applications.
Regarding Claim 6: RYU as modified teaches a semiconductor device structure as set forth in claim 5 as above. The combination of RYU and Liaw further teaches wherein the first dielectric material (240A) is disposed between the first and second fin structures (206/208) (see Liaw, Figs.8 and 11 as shown above).
Claim(s) 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (U.S. 2024/0055425 A1, hereinafter refer to RYU) in view of Lee (U.S. 2024/0321874 A1, hereinafter refer to Lee).
Regarding Claim 8: RYU discloses a semiconductor device structure (see RYU Figs.13-14 as shown above and ¶ [0002]), comprising:
a first source/drain region (120) (note: the source/drain regions 120 may be disposed on the active pattern 115 and positioned on both (opposing) sides of the gate lines (e.g., GL1, GL2, and GL3)) (see RYU Figs.13-14 as shown above and ¶ [0044]);
a second source/drain region (120) disposed adjacent the first source/drain region (120) along a first direction (note: the source/drain regions 120 may be disposed on the active pattern 115 and positioned on both (opposing) sides of the gate lines (e.g., GL1, GL2, and GL3)) (see RYU Figs.13-14 as shown above and ¶ [0044]);
a third source/drain region (120) disposed adjacent the first source/drain region (120) along a second direction substantially perpendicular to the first direction (note: the source/drain regions 120 may be disposed on the active pattern 115 and positioned on both (opposing) sides of the gate lines (e.g., GL1, GL2, and GL3)) (see RYU Figs.13-14 as shown above and ¶ [0044]);
first and second gate spacers (164/166 of GL1/GL2) disposed between the first and third source/drain regions (120) (see RYU Figs.13-14 as shown above); and
a first dielectric material (170) disposed between the first and second gate spacers (164 of GL1/GL2) (see RYU Figs.13-14 as shown above).
RYU is silent upon explicitly disclosing wherein a top surface of the first dielectric material has a cross shape.
For support see Lee, which teaches wherein a top surface of the first dielectric material (150/190) has a cross shape (see Lee, Figs.3A-3B as shown below and ¶ [0004]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of RYU and Lee to enable top surface of the first dielectric material to have a cross shape as taught by Lee in order to improve reliability even when aspect ratios of components included in the device region increase.
Regarding Claim 9: RYU as modified teaches a semiconductor device structure as set forth in claim 8 as above. The combination of RYU and Lee further teaches wherein the first dielectric material (170) extends into the first and second gate spacers (164/166 of GL1/GL2) (see RYU Figs.13-14 as shown above).
Regarding Claim 10: RYU as modified teaches a semiconductor device structure as set forth in claim 8 as above. The combination of RYU and Lee further teaches wherein the first dielectric material (150/190) comprises a horizontal portion and a vertical portion (see Lee, Figs.3A-3B as shown above).
Regarding Claim 11: RYU as modified teaches a semiconductor device structure as set forth in claim 10 as above. The combination of RYU and Lee further teaches wherein the first dielectric material (150/190) further comprises a connecting portion connecting the horizontal portion and the vertical portion (see Lee, Figs.3A-3B as shown above).
Regarding Claim 12: RYU as modified teaches a semiconductor device structure as set forth in claim 11 as above. The combination of RYU and Lee further teaches wherein the connecting portion has a curved surface (see Lee, Figs.3A-3B as shown above).
Note: the configuration of the claimed disposable connecting portion was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed first dielectric material was significant.
Regarding Claim 13: RYU as modified teaches a semiconductor device structure as set forth in claim 8 as above. The combination of RYU and Lee further teaches wherein a first gate electrode layer (165 of GL1) disposed between the first and second gate spacers (164/166 of GL1/GL2) and a second gate electrode layer (165 of GL2) disposed between the first and second gate spacers (164/166 of GL1/GL2), wherein the first dielectric material (170) is disposed between the first and second gate electrode layers (165 of GL1/GL2) (see RYU Figs.13-14 as shown above).
Regarding Claim 14: RYU as modified teaches a semiconductor device structure as set forth in claim 13 as above. The combination of RYU and Lee further teaches wherein first and second fin structures (FS1/FS2) (see RYU Figs.13-14 as shown above).
Regarding Claim 15: RYU as modified teaches a semiconductor device structure as set forth in claim 14 as above. The combination of RYU and Lee further teaches wherein the first dielectric material (170) is disposed between the first and second fin structures (see RYU Figs.13-14 as shown above).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (U.S. 2024/0055425 A1, hereinafter refer to RYU) and Lee (U.S. 2024/0321874 A1, hereinafter refer to Lee) as applied to claim 15 above, and further in view of Liaw (U.S. 2021/0202498 A1, hereinafter refer to Liaw).
Regarding Claim 16: RYU as modified teaches a semiconductor device structure as applied to claim 15 above. The combination of RYU and Lee is silent upon explicitly disclosing wherein a second dielectric material disposed adjacent the third source/drain region, wherein the second dielectric material extends across the first and second fin structures.
For support see Liaw, which teaches wherein a second dielectric material (240A) disposed adjacent the third source/drain region (214), wherein the second dielectric material (240A) extends across the first and second fin structures (206/208) (see Liaw, Figs.8 and 11 as shown above and ¶ [0020]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of RYU, Lee, and Liaw to enable the second dielectric material to be disposed adjacent the third source/drain region, wherein the second dielectric material extends across the first and second fin structures as taught by Liaw allowing better gate control, lowered leakage current, and improved scaling capability for various IC applications.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (U.S. 2024/0055425 A1, hereinafter refer to RYU) as applied to claim 17 above, and further in view of Lee (U.S. 2024/0321874 A1, hereinafter refer to Lee).
Regarding Claim 20: RYU discloses a method for forming a semiconductor device structure as applied to claim 17 above. RYU is silent upon explicitly disclosing wherein the opening has a cross shape when viewed from top.
For support see Lee, which teaches wherein the opening (150/190) has a cross shape when viewed from top (see Lee, Figs.3A-3B as shown below and ¶ [0004]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of RYU and Lee to enable the opening having a cross shape when viewed from top as taught by Lee in order to improve reliability even when aspect ratios of components included in the device region increase.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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