Prosecution Insights
Last updated: October 01, 2026
Application No. 18/765,710

ADVANCED-PACKAGING HIGH-VOLUME-MODE DIGITAL-LITHOGRAPHY-TOOL

Non-Final OA §103
Filed
Jul 08, 2024
Priority
Jul 25, 2022 — continuation of 12/032,284
Examiner
SULLIVAN, CALEEN O
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
1012 granted / 1142 resolved
+20.6% vs TC avg
Moderate +11% lift
Without
With
+11.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
22 currently pending
Career history
1148
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
19.5%
-20.5% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1142 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanaoka (US 2010/0159372) in view of Gopalan. (US 2020/0194290). Kanaoka discloses a substrate processing apparatus. Kanaoka discloses a substrate processing apparatus 500 includes an indexer block 9, an anti-reflection film processing block 10, a resist film processing block 11, a development processing block 12, a resist cover film processing block 13, a resist cover film removal block 14, and an interface block 15. (Para, 0071). Kanaoka discloses an exposure device 16 is arranged adjacent to the interface block 15 and it subjects a substrate W to exposure processing by means of a liquid immersion method. (Para, 0071). Kanaoka discloses the indexer block 9 includes a main controller (controller) 30 that controls the operation of each of the processing blocks, an alarm device 30b, a plurality of carrier platforms 40, and an indexer robot IR, which has a hand IRH provided for receiving and transferring the substrates W. (Para, 0073; Fig.1). Kanaoka discloses the anti-reflection film processing block 10 includes thermal processing groups 100 and 101 for anti-reflection film, a coating processing group 50 for anti-reflection film, and a first central robot CR1. (Para, 0074; Fig.1). Kanaoka discloses the first central robot CR1 has hands CRH1 and CRH2 provided one above the other for receiving and transferring the substrates W. (Para, 0074; Fig.1). These disclosures and the illustrations of Figure 1 teach and/or suggest the limitation of claim 2, ‘A substrate packaging system, comprising: a robotic transfer system comprising a plurality of robotic arms…’ Kanaoka discloses the substrate platforms PASS1 and PASS2 is provided with an optical sensor (not illustrated) for detecting the presence or absence of the substrate W and this enables determination whether or not the substrate W is placed on the substrate platform PASS1 or PASS2. (Para, 0076; Fig.1). Kanaoka discloses each of the substrate platforms PASS1 and PASS2 has a plurality of support pins secured thereto and substrate platforms PASS3 to PASS13 are similarly provided with an optical sensor and support pins. (Para, 0076; Fig.1). These disclosures and the illustration of Figure 1 teach and/or suggest the limitation of claim 2, ‘ A substrate packaging system, comprising: …at least one metrology station comprising: a topology sensor…’ and the limitation of claim 7. Kanaoka discloses the resist film processing block 11 includes thermal processing groups 110 and 111 for resist film, a coating processing group 60 for resist film, and a second central robot CR2, which has hands CRH3 and CRH4 provided one above the other for receiving and transferring the substrates W. (Para, 0077; Fig.1). Kanaoka discloses the development processing block 12 includes thermal processing groups 120 and 121 for development, a development processing group 70, and a third central robot CR3, which has hands CRH5 and CRH6 provided one above the other for receiving and transferring the substrates W. (Para, 0079; Fig.1). Kanaoka discloses the resist cover film processing block 13 includes thermal processing groups 130 and 131 for resist cover film, a coating processing group 80 for resist cover film, and a fourth central robot CR4 which has hands CRH7 and CRH8 provided one above the other for receiving and transferring the substrates W. (Para, 0081; Fig.1). Kanaoka discloses the resist cover film removal block 14 includes thermal processing groups 140 and 141 for post-exposure bake, a removal processing group 90 for resist cover film, and a fifth central robot CR5, which has hands CRH9 and CRH10 provided one above the other for receiving and transferring the substrates W. (Para, 0083). Kanaoka explains the thermal processing group 141 is adjacent to the interface block 15, and includes substrate platforms PASS11 and PASS12. (Para, 0083; Fig.1). Kanaoka discloses the interface block 15 includes a first inspection unit EE1, a sending buffer unit SBF, a first cleaning/drying processing unit SD1, a sixth central robot CR6, an edge exposure unit EEW, a second inspection unit EE2, a return buffer unit RBF, placement/cooling units PASS-CP (hereinafter abbreviated as P-CP), a substrate platform PASS13, an interface transport mechanism IFR, and a second cleaning/drying processing unit SD2. (Para, 0085; Fig.1). Kanaoka explains the first inspection unit EE1 inspects the state of the substrate W before exposure processing, and the second inspection unit EE2 inspects the state of the substrate W after exposure processing. (Para, 0086). These disclosures and the illustrations of Figure 1 teach and/or suggest the limitation of claim 2, ‘ A substrate packaging system, comprising: …a substrate aligner that aligns a substrate to a predetermined angular position; at least one metrology station comprising: …a die pattern sensor… and a printing station.’ Moreover, these disclosures and illustrations teach and/or suggest the limitation of claims 3, 6 10-11, and 19-20. Kanaoka discloses the coating processing group 80 in the resist cover film processing block 13 has a vertical stack of three coating units COV and each of the coating units COV includes a spin chuck 81 for rotating the substrate W with the substrate W held in a horizontal attitude by suction, and a supply nozzle 82 for supplying a coating liquid for a resist cover film to the substrate W held on the spin chuck 81. (Para, 0093). Kanaoka discloses the edge exposure unit EEW includes a spin chuck 98 for rotating the substrate W with the substrate held in a horizontal attitude by suction, and a light irradiator 99 for exposing a peripheral portion of the substrate W held on the spin chuck 98. (Para, 0096; Fig.1). These disclosures and illustrations teach and/or suggest the limitation of claims 4-5, 12-13, 15 and 18. Kanaoka discloses each of the thermal processing groups 130 and 131 in the resist cover film processing block 13 has a stack of two heating units HP and two cooling units CP. (Para, 0100; Fig.3). Kanaoka also discloses in the resist cover film removal block 14, the thermal processing group 140 has a vertical stack of two heating units HP and two cooling units CP, and the thermal processing group 141 has a vertical stack of two heating units HP, two cooling units CP, and substrate platforms PASS11 and PASS12. (Para, 0101; Fig.3). These disclosures teach and/or suggest the limitation of claim 14. Still, the disclosures and illustrations of Kanaoka fail to teach and/or suggest the limitation of claim 2, ‘A substrate packaging system, comprising: …an adaptive chucking mechanism that is communicatively coupled with the topology sensor…’ However, the disclosures of Kanaoka in view of the disclosures of Gopalan provide such teachings. Gopalan discloses an apparatus for measuring chucking force and methods of using such apparatuses. (Para, 0007). Gopalan discloses the apparatus for measuring a chucking force comprises a substrate having a chucking surface, where the chucking surface is the surface that is supported by a chuck. (Para, 0007). Gopalan also discloses the apparatus further comprises a plurality of sensors over the chucking surface, where the plurality of sensors are thin film sensors with a thickness that is less than a thickness of the substrate. (Para, 0007). Gopalan explains the apparatus further comprises a wireless communication module electrically coupled to each of the plurality of sensors. (Para, 0007). Gopalan discloses the sensors measure the chucking force and the system may further comprise a wireless communication module electrically coupled to the plurality of sensors, where the wireless communication module transmits chucking force data outside of the chamber. (Para, 0008). The disclosures of Kanaoka further in view of these disclosures of Gopalan teach and/or suggest the limitation of claim 2, ‘ A substrate packaging system, comprising: …an adaptive chucking mechanism that is communicatively coupled with the topology sensor…’ Gopalan also discloses various embodiments may also comprise a method of optimizing a semiconductor fabrication process recipe. (Para, 0009). Gopalan explains the method comprises placing a substrate having a plurality of thin film sensors on a chucking surface of the substrate on a support surface in a processing tool and may also comprise securing the substrate to the support surface with a chucking force, where the plurality of thin film sensors provide a measurement of the chucking force across a surface of the substrate. (Para, 0009). Gopalan discloses the method may further comprise executing a process recipe in the processing tool, and obtaining chucking force measurements from the plurality of sensors during execution of the process recipe. (Para, 0009). Gopalan discloses the method may further comprise using the chucking force measurements to modify the process recipe. (Para, 0009). The disclosures of Kanaoka in view of these disclosures teach and/or suggest the limitation of claims 9, 16-17 and 21. Gopalan also discloses the support surface 130 may be an electrostatic chuck (ESC), a vacuum chuck, a heater pedestal, or any other support surface used in semiconductor manufacturing environments or it may be one or more of a Coulombic chuck, a Johnson-Rahbek (J-R) chuck, a monopolar ESC, and a bipolar ESC. (Para, 0024; Fig.1). The disclosures of Kanaoka in view of these disclosures teach and/or suggest the limitation of claim 8. It would have been obvious to one of ordinary skill in the art at the time of filing of the present application by Applicant to modify the disclosures of Kanaoka in view of the disclosures of Gopalan because both are directed to analogous methods of processing a semiconductor substrate and Gopalan discloses a method of measuring and adjusting checking force on a wafer so that substrates being processed are not over-chucked and damage to the chucking surface of the substrate (i.e., the backside of the wafer) being processed and to the chuck itself is avoided along with decreasing particle generation and improving the useable lifespan of the chuck. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEEN O SULLIVAN whose telephone number is (571)272-6569. The examiner can normally be reached Mon-Fri: 7:30 am-4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Jul 08, 2024
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+11.4%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1142 resolved cases by this examiner. Grant probability derived from career allowance rate.

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