DETAILED ACTION
This Office Action is in response to Applicant’s application 18/765,940 filed on July 8, 2023 in which claims 1 and 7-22 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on July 8, 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on December 26, 2025; May 20, 2025 and October 22, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 8-9 which recite the limitation "forming the plurality of isolation walls" in respective lines 1. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 8 which recites the limitation ‘the recesses’ at line 4. There is insufficient antecedent basis for this limitation in the claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 7-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,033,887 (‘887). Although the claims at issue are not identical, they are not patentably distinct from each other as discussed below.
Table 1 – Comparison of Pending Claim to ‘887 Claim
Pending Claim
’887 Claim
1. A method of fabricating a display, comprising:
providing a substrate having an array of light emitting diodes disposed thereon;
moving the substrate relative to a backplane having backplane circuitry to bring the array of light emitting diodes into contact with the backplane;
electrically integrating the array of light emitting diodes with the backplane circuitry of the backplane;
removing the substrate such that the array of light emitting diodes remain on the backplane;
after removing the substrate,
depositing a plurality of isolation walls on the backplane so that the isolation walls separate adjacent light emitting diodes and extend above the light emitting diodes;
1. A method of fabricating a multi-color display, comprising:
forming a plurality of isolation walls on a backplane that has backplane circuitry;
providing a substrate having an array of light emitting diodes disposed thereon;
moving the substrate relative to the backplane to bring the array of light emitting diodes into contact with the backplane
such that the isolation walls formed on the backplane separate adjacent light emitting diodes and extend above a height of the light emitting diodes;
electrically integrating the array of light emitting diodes with the backplane circuitry of the backplane;
removing the substrate such that the array of light emitting diodes remain on the backplane;
disposing a first photo-curable fluid that includes a first color conversion agent into recesses between the isolation walls and over a first plurality of light emitting diodes from the array of light emitting diodes; and
curing the first photo-curable fluid over the first plurality of light emitting diodes to form a first color conversion layer over each of the first plurality of light emitting diodes to convert light from the first plurality of light emitting diodes to light of a first color.
7. The method of claim 1, wherein moving the substrate relative to the backplane causes the plurality of isolation walls to extend into recesses in the substrate.
7. The method of claim 1, wherein moving the substrate relative to the backplane causes the plurality of isolation walls to extend into recesses in the substrate.
8. The method of claim 1, wherein forming the plurality of isolation walls comprises deposition of a photoresist on the backplane, patterning of the photoresist by photolithography, and development to remove the portions of the photoresist corresponding to the recesses.
8. The method of claim 1, wherein forming the plurality of isolation walls comprises deposition of a photoresist on the backplane, patterning of the photoresist by photolithography, and development to remove portions of the photoresist corresponding to the recesses.
9. The method of claim 1, wherein forming the plurality of isolation walls comprises deposition of a metal and lithography.
9. The method of claim 1, wherein forming the plurality of isolation walls comprises deposition of a metal and lithography.
10. The method of claim 1, wherein the isolation walls are formed to have a height of 3 to 20 μm.
10. The method of claim 1, wherein the isolation walls are formed to have a height of 3 to 20 μm.
11. The method of claim 1, wherein the isolation walls are formed to have a width W of 2 to 10 μm.
11. The method of claim 1, wherein the isolation walls are formed to have a width W of 2 to 10 μm.
12. The method of claim 1, wherein the isolation walls are formed to have an aspect ratio of 1.5:1 to 5:1.
12. The method of claim 1, wherein the isolation walls are formed to have an aspect ratio of 1.5:1 to 5:1.
13. The method of claim 1, wherein light emitting diodes of the array of light emitting diodes are semiconductor micro-LEDs.
13. The method of claim 1, wherein light emitting diodes of the array of light emitting diodes are semiconductor micro-LEDs.
14. The display of claim 13, wherein the semiconductor micro-LEDs comprise III-V semiconductor LEDs.
14. The method of claim 13, wherein the semiconductor micro-LEDs comprise III-V semiconductor LEDs.
15. The method of claim 1, comprising dispensing a first photo-curable fluid to fill gaps between the light emitting diodes and the isolation walls.
15. The method of claim 1, wherein dispensing the first photo-curable fluid fills gaps between the light emitting diodes and the isolation walls.
16. The method of claim 1, wherein material of the isolation wall is absent from between the backplane and the light emitting diodes.
16. The method of claim 1, wherein material of the isolation walls is absent from between the backplane and the light emitting diodes.
17. The method of claim 1, further comprising:
disposing a first photo-curable fluid that includes a first color conversion agent into recesses between isolation walls and over a first plurality of light emitting diodes from the array of light emitting diodes; and
curing the first photo-curable fluid over the first plurality of light emitting diodes to form a first color conversion layer over each of the first plurality of light emitting diodes to convert light from the first plurality of light emitting diodes to light of a first color.
From claim 1
disposing a first photo-curable fluid that includes a first color conversion agent into recesses between the isolation walls and over a first plurality of light emitting diodes from the array of light emitting diodes; and
curing the first photo-curable fluid over the first plurality of light emitting diodes to form a first color conversion layer over each of the first plurality of light emitting diodes to convert light from the first plurality of light emitting diodes to light of a first color.
18. The method of claim 17, further comprising: disposing a second photo-curable fluid that includes a second color conversion agent into recesses between isolation walls and over a second plurality of light emitting diodes from the array of light emitting diodes; and curing the second photo-curable fluid over the second plurality of light emitting diodes to form a second color conversion layer over each of the second plurality of light emitting diodes to convert light from the second plurality of light emitting diodes to light of a second color.
2. The method of claim 1, further comprising: disposing a second photo-curable fluid that includes a second color conversion agent into recesses between isolation walls and over a second plurality of light emitting diodes from the array of light emitting diodes; and curing the second photo-curable fluid over the second plurality of light emitting diodes to form a second color conversion layer over each of the second plurality of light emitting diodes to convert light from the second plurality of light emitting diodes to light of a second color.
19. The method of claim 18, further comprising: disposing a third photo-curable fluid that includes a third color conversion agent into recesses between isolation walls and over a third plurality of light emitting diodes from the array of light emitting diodes; and curing the third photo-curable fluid over the third plurality of light emitting diodes to form a third color conversion layer over each of the third plurality of light emitting diodes to convert light from the third plurality of light emitting diodes to light of a third color.
3. The method of claim 2, further comprising: disposing a third photo-curable fluid that includes a third color conversion agent into recesses between isolation walls and over a third plurality of light emitting diodes from the array of light emitting diodes; and curing the third photo-curable fluid over the third plurality of light emitting diodes to form a third color conversion layer over each of the third plurality of light emitting diodes to convert light from the third plurality of light emitting diodes to light of a third color.
20. The method of claim 19, wherein the first color, second color and third color are selected from blue, green and red.
4. The method of claim 3, wherein the first color, second color and third color are selected from blue, green and red.
21. The method of claim 15, wherein dispensing the photo-curable fluid includes one or more of a spin-on, dipping, spray-on, or inkjet process.
5. The method of claim 1, wherein dispensing the first photo-curable fluid includes one or more of a spin-on, dipping, spray-on, or inkjet process.
22. The method of claim 21, wherein dispensing the first photo-curable fluid comprises an inkjet process.
6. The method of claim 5, wherein dispensing the first photo-curable fluid comprises an inkjet process.
Regarding claim 1 and referring to Table 1, Examiner notes both claims teach providing a substrate with an array of LEDs, and moving a backplane to contact the substrate and removing the substrate. Examiner notes that depositing a plurality of isolation walls on the backplane appears to be a species forming a plurality of isolation walls on a backplane and further that each claim provides that the isolation walls are separate from and above the LEDs. Pending claim 1 provides that isolation walls are formed after substrate removal while claim 1 of the ‘887 provides that isolation walls are formed before substrate removal and to the difference between the claims appears to merely and order of steps in that Examiner cannot discern any structural difference between the device produced by pending method claim 1 and method claim 1 of the ‘887 patent. Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to modify the order of the steps because selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. In re Gibson, 39 F.2d 975, (CCPA 1930), In re Hurhans, 154 F.2d 690 (CCPA 1946).
Regarding claims 7-16, Examiner notes this subject matter appears to be described in claims 7-16 of the ‘887 patent.
Regarding claim 17, Examiner notes claim of the ‘887 patent recites this subject matter.
Regarding claims 18-22, Examiner notes claims 2-6 of the ‘887 patent recite this subject matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 10-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as anticipated by U.S. 2020/0295224 (Yanagawa) or, in the alternative, under 35 U.S.C. 103 as obvious over Yanagawa and U.S. 2019/0237452 (Kuo).
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Regarding claim 1 and referring to annotated Figures 3A-3D, 4A-4C and 5A-5D. Yanagawa discloses a method of fabricating a display, comprising:
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providing a substrate, sapphire not shown but described at [0032], having an array of light emitting diodes, 4 [0033-34] disposed thereon;
moving the substrate, as shown and described [0042], relative to a backplane, 5 [0042], having backplane circuitry, [0021], to bring the array of light emitting diodes into contact with the backplane, as shown;
electrically integrating the array of light emitting diodes with the backplane circuitry of the backplane, as shown and described at [0041-42];
removing the substrate such that the array of light emitting diodes remain on the backplane, as shown;
after removing the substrate, [0042], depositing a plurality of isolation walls, 3
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[0048-82], on the backplane, as shown, so that the isolation walls separate adjacent light emitting diodes, as shown, and extend above the light emitting diodes, as shown, where Examiner has interpreted depositing as to lay down or to let fall, see definition of deposit downloaded from URL <DEPOSIT Definition & Meaning - Merriam-Webster> on August 3, 2026.
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If it is determined Yanagawa does not teach depositing isolation walls on the backplane, Examiner notes Kuo is directed to methods of improving isolation walls for displays. At annotated Figure 1A, Kuo teaches depositing a plurality of isolation walls, 142a1 [0037], on the backplane, 110, so that the isolation walls separate adjacent light emitting diodes, 130, and extend above the light emitting diodes, as shown.
At [0037-38] Kuo teaches:
[0037] Additionally, a material of the first bank portions 142a1, 142a2, 142a3 and 142a4 and the second bank portions 144a1, 144a2, 144a3 and 144a4 of the bank structures 140a1, 140a2, 140a3 and 140a4 may be the same or different, which can be comprised of any patternable gel material, wherein the material comprises, for example, a black photoresist, a white photoresist, a transparent material doped with a scattering material, a transparent material coated with a reflective film, or a photo spacer. For instance, referring to FIG. 1A, if the first bank portion 142a1 comprises a black photoresist and the second bank portion 144a1 comprises a white photoresist, the first bank portion 142a1 can absorb the light with larger angle emitted from the micro light-emitting diodes 130 to the array substrate 110, so as to prevent the light with larger angle from generating a specific angle reflection after reflecting from the array substrate 110, thereby affecting visual effects. The second bank portions 144a1 can guide lights emitted from side walls of the micro light-emitting diodes 130 to be transmitted along a normal direction so as to improve the light-emitting efficiency of the micro light-emitting diodes 130 and adjust the light-emitting viewing angle of the micro light-emitting diodes 130.
[0038] In short, since the display device 100a of the embodiment comprises the bank structures 140a1, the optical cross-talk phenomenon generated by the micro light-emitting diodes 130 arranged in an array on the array substrate 110 can be effectively reduced. Thereby, the optical display performance of the display device 100a of the embodiment can be effectively improved. Additionally, the bank structures 140a1 are composed of the first bank portion 142a1 and the second bank portion 144a1 connected to each other, and thus the material of the first bank portion 142a1 and the second bank portion 144a1, the angle design of the first included angle A11 and the second included angle A12 and the position where the first bank portion 142a1 and the second bank portion 144a1 disposed can be chosen by users according to their needs. For example, the first bank portion 142a1 and the second bank portion 144a1 are both disposed above the array substrate 110 or the opposite substrate 120. Alternatively, at least one of the first bank portion 142a1 and the second bank portion 144a1 is disposed above the array substrate 110, and at least another one of the first bank portion 142a1 and the second bank portion 144a1 is disposed above the opposite substrate 120. In other words, the bank structures 140a1 of the embodiment has a wider flexibility of the design, and the micro light-emitting diodes 130 may have better light-emitting efficiency by the design of the bank structures 140a1, such that the display device 100a of the embodiment has a better optical display performance.
Kuo teaches that when the isolation wall is deposited on the backplane that it may be configured to reduce optical cross talk of the LEDs thus improving the quality of the display.
Taken as a whole the prior art is directed to methods of forming displays with improved quality. An artisan would find it desirable to reduce the optical cross talk in an LED display to improve image quality. Accordingly, it would have been obvious to configure the method of claim 1 comprising depositing a plurality of isolation walls on the backplane, as taught by Kuo, to reduce optical cross talk of the LEDs, as taught by Kuo and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 10 which depends upon claim 1, Yanagawa teaches the isolation walls are formed to have a height of 3 to 20 μm at [0044]
Regarding claim 11 which depends upon claim 1, Yanagawa teaches the ratio of the height to width of the isolation walls is 3 or more [0044]. Thus for a 20 micron height the thickness is 20/3 ~7 or more microns and so Yanagawa teaches the isolation walls are formed to have a width W of 2 to 10 μm.
Regarding claim 12 which depends upon claim 1, Yanagawa teaches the isolation walls are formed to have an aspect ratio of 1.5:1 to 5:1 at [0033].
Regarding claim 13 which depends upon claim 1, Yanagawa teaches light emitting diodes of the array of light emitting diodes are semiconductor micro-LEDs at [0022].
Regarding claim 14 which depends upon claim 13, Yanagawa teaches the semiconductor micro-LEDs comprise III-V semiconductor LEDs at [0022].
Regarding claim 16 which depends upon claim 1, Yanagawa teaches material of the isolation wall is absent from between the backplane and the light emitting diodes at Figure 5D.
Conclusion
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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