DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Objections 3
III. Double Patenting 3
A. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20, respectively, of U.S. Patent No. 12,074,125. 5
B. Claims 1, 4, 5, and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4, 4, 5, and 10-20 of U.S. Patent No. 11,637,078, respectively. 5
C. Claims 1-3 and 6-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 11,637,078 in view of US 9,425,149 (“Jiang”). 6
D. Claims 10-13 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-10 and 13, respectively, of U.S. Patent No. 10,930,603. 7
IV. Allowable Subject Matter 8
A. Claim 1 8
B. Claim 10 11
C. Claim 16 21
Conclusion 22
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Objections
Claim 10 is objected to because of the following informalities:
In the third to last line of claim 10, replace “isolate” with “isolates” for correct subject-verb agreement.
Appropriate correction is required.
III. Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
A. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20, respectively, of U.S. Patent No. 12,074,125.
Although the claims at issue are not identical, they are not patentably distinct from each other. In this regard, each of claims 1-20 of the ‘125 patent is directed to a semiconductor package and each of instant claims 1-20 is directed to a method of making a semiconductor package. Each of the structural limitations of claims 1-20 of the ‘125 patent is identical to the structural limitations recited in claims 1-20 of the Instant Application, respectively. The only distinction between the respective claims is that instant claims 1-20 include the terms, “forming” or “providing” of each of the structural limitations recited in claims 1-20 of the ’125 patent.
It is implicit that in order for each feature of the semiconductor packages claimed in the ‘125 patent to exist, then each of the structural limitations must have been formed or provided. As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form or to provide each of the structural limitations of claims 1-20 of the ‘125 patent, in order to make the semiconductor package(s) recited in claims 1-20 of the ‘125 patent.
B. Claims 1, 4, 5, and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4, 4, 5, and 10-20 of U.S. Patent No. 11,637,078, respectively.
Although the claims at issue are not identical, they are not patentably distinct from each other because, with regard to the structural limitations, instant claims 1, 4, and 5 are merely broader versions of the corresponding structural limitations recited in claims 4, 4, and 5 of the ‘078 patent, respectively. In addition, instant claims 10-20 are merely broader versions of claims 10-20 of the ‘078 patent, respectively.
As above, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form or to provide each of the structural limitations of claims 4, 4, 5, and 10-20 of the ‘078 patent, in order to make the semiconductor package(s) recited in claims 4, 4, 5, and 10-20 of the ‘078 patent.
C. Claims 1-3 and 6-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 11,637,078 in view of US 9,425,149 (“Jiang”).
With regard to the structural limitations, instant claim 1 is broader than claim 1 of the ‘078 patent except that instant claim 1 includes the limitation,
wherein the at least one signal path comprises a quadrantal signal path including a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path
while, by contrast, claim 1 of the ‘078 patent includes the broader limitation,
wherein the at least one signal path comprises a differential signal path including a first transmission path and a second transmission path.
The Instant Application explains that a quadrantal signal path is a pair of differential signal paths (Instant Specification: ¶ 38).
Thus, claim 1 of the ‘078 patent does not include the quadrantal signal path.
Jiang, like claim 1 of the ‘078 patent, teaches a semiconductor package including signal paths shielded by a grounded metal structure 304 surrounding the signal paths (Jiang: Figs. 2, 5; col. 5, line 60 to col. 6, line 11). Jiang further teaches that a two pairs of differential signal paths, i.e. 300-1, 300-2 and 302-1, 302-2, can have the cross-talk reduced by the same, surrounding grounded metal structure 304 (Jiang: Fig. 5; col. 6, lines 1-41).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the signal path of claim 1 of the ‘078 patent to include two differential signal paths, in order to make more efficient use of the shielding function of the claimed “ground shielding layer” that surrounds the signal path which would, thereby reducing the amount of material and processing to form said ground shielding layer than would be required if each differential signal path were surrounded by the ground shielding layer. In addition, the quadrantal signal path is obvious in view of the differential signal path because the courts have held that mere duplication of parts has no patentable significance unless a new or unexpected result is produced. See In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). There is no evidence of record of an unexpected result for using a shielded quadrantal signal path versus a shielded differential signal path.
With regard to the structural limitations, instant claims 2, 3, and 6-9 are essentially the same, if not verbatim duplicates of claim 2, 3, and 6-9 of the ‘078 patent, respectively.
As above, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form or to provide each of the structural limitations of claim 1-3 and 6-9 of the ‘149 patent, in order to make the semiconductor package(s) recited in claim -3 and 6-9 of the ‘149 patent.
D. Claims 10-13 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-10 and 13, respectively, of U.S. Patent No. 10,930,603.
Although the claims at issue are not identical, they are not patentably distinct from each other because, with regard to the structural limitations, each of instant claims 10-13 and 15 is merely broader than each of the respective claims 7-10 and 13 of the ‘603 patent by omission of selected features.
As above, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form or to provide each of the structural limitations of claims 7-10 and 13, of the ‘603 patent, in order to make the semiconductor package(s) recited in claims 7-10 and 13 of the ‘603 patent.
IV. Allowable Subject Matter
If Applicant files the terminal disclaimers to overcome the double patenting rejections, then claims 1-20 would be allowable.
The following is a statement of reasons for the indication of allowable subject matter:
A. Claim 1
Claim 1 reads,
1. A method of forming a semiconductor package, comprising:
[1] providing a first semiconductor device;
[2] providing a second semiconductor device, wherein the second semiconductor device includes a continuous ground shielding; and
[3] forming a ground shielded transmission path that couples the first semiconductor device to the second semiconductor device, the ground shielded transmission path comprising:
[4] at least one signal path extending longitudinally between a first end and a second end, the at least one signal path including an electrically conductive material;
[5] a first insulating layer disposed over the signal path longitudinally between the first end and the second end, wherein the first insulating layer includes an electrically insulating material; and
[6] a ground shielding layer disposed over the insulating material longitudinally between the first end and the second end of the signal path, wherein the ground shielding layer includes an electrically conductive material, and
[7] wherein each of the continuous ground shielding and the ground shielding layer are coupled to ground,
[8] wherein the at least one signal path comprises a quadrantal signal path including a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path.
The closest prior art reference to the elements of claim 1 are JP 2015-060909, which shares patent family member, US 2016/0173803 (collectively “Fukuoka”). The pre-grant application publication, US 2016/0173803, is being used as the translation for JP 2015-060909. As such, all citations to Fukuoka are from the US publication.
With regard to claim 1, Fukuoka discloses, generally in Figs. 1-3,
1. A method of forming a semiconductor package, comprising:
[1] providing a first semiconductor device 31 [¶¶ 27-29];
[2] providing a second semiconductor device 32, wherein the second semiconductor device includes a continuous ground shielding [i.e. the wiring 324 in wiring layer 323 connected between the ground potential within the “second device manufacturing region 322 of the second semiconductor chip 32” (¶ 51, infra) and mesh shield 332 shown in Figs. 2 and 3]; and
[3] forming a ground shielded transmission path 331/332 [¶¶ 45-54] that couples the first semiconductor device 31 to the second semiconductor device 32, the ground shielded transmission path 331/332 comprising:
[4] at least one signal path 331 extending longitudinally between a first end [top side of the “connection region 33” (¶ 40), i.e. the claimed “inter fan-out layer: (infra)] and a second end [bottom side of the “connection region 33”], the at least one signal path 331 including an electrically conductive material [¶ 46];
[5] a first insulating layer [“insulating member” (¶ 47) shown but not labeled] disposed over the signal path 331 longitudinally between the first end and the second end [¶ 47: “In FIG. 2, spaces that are present between the shield 332 and the bumps 331 are filled with an insulating member, such as resin or an adhesive.”], wherein the first insulating layer [“insulating member”] includes an electrically insulating material [i.e. “resin or adhesive” (id.)]; and
[6] a ground shielding layer 332 disposed over the [electrically] insulating material [i.e. “resin or adhesive” (id.)] longitudinally between the first end and the second end of the signal path 331, wherein the ground shielding layer 332 includes an electrically conductive material [¶ 46], and
[7] wherein each of the continuous ground shielding and the ground shielding layer 332 are coupled to ground,
[8] … [not taught] …
With regard to feature [6] of claim 1, Fukuoka states,
[0046] Electric potentials (hereinafter referred to as “fixed electric potentials”) with constant values are provided within the first semiconductor chip 31 and the second semiconductor chip 32. A shield 332 is a noise shielding layer that is connected to a fixed electric potential (for example, the ground) of at least one of the first semiconductor chip 31 and the second semiconductor chip 32. …
[0051] As illustrated in FIG. 2, the shield 332 is manufactured at positions where the bumps 331 are sandwiched (the bumps 331 are surrounded) as can also be understood by looking at the sectional view of the semiconductor device 3 as seen from a direction in which the first semiconductor chip 31 and the second semiconductor chip 32 are stacked. As described above, the shield 332 is connected to, for example, the fixed electric potentials, such as the ground, within the manufactured semiconductor chips. More specifically, the shield 332 is connected to the fixed electric potentials within the first device manufacturing region 312 of the first semiconductor chip 31 and the second device manufacturing region 322 of the second semiconductor chip 32. In FIG. 3, a central shield 332b is connected to the fixed electric potential [“such as ground” (supra)] within the first device manufacturing region 312 of the first semiconductor chip 31 [by means of wiring 314; ¶ 50]. A case where shields 332a and 332c at both ends are respectively connected to fixed electric potentials [“such as ground” (supra)] within respective second device manufacturing regions 322 of the second semiconductor chip 32 [by means of wiring 324; ¶ 50] is illustrated.
(Fukuoka: ¶¶ 46 and 51; emphasis added)
Thus the grid or mesh shield 332, shown in overhead (Fig. 2) and in cross-section (Fig. 3), is physically and electrically connected to the ground potentials in the respective first 312 and second 322 “device manufacturing regions” of each of the first 31 and second 32 semiconductor devices by means of the respective wiring layers 314 and 324. As such, each of the wirings 314, 324 and the mesh shield 332 are all at ground potential, as required by feature [5c].
Thus the prior art does not reasonably teach or suggest—in the context of claim 1—feature [8]:
[8] wherein the at least one signal path comprises a quadrantal signal path including a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path.
Claims 2-9 would be allowable at least for including the same allowable limitation by depending from claim 1.
B. Claim 10
Claim 10 reads,
10. A method of making a semiconductor package, comprising:
[1] providing a first semiconductor device;
[2] providing a second semiconductor device positioned below the first semiconductor device;
[3a] forming an inter fan-out layer between the first semiconductor device and the second semiconductor device, wherein the inter fan-out layer comprises
[3b] a semiconductor die containing an active device therein,
[3c] a first ground shielding structure within the semiconductor die and disposed about the active device so as to isolate the active device from radiation signals;
[4a] forming a ground shielded transmission path that couples the first semiconductor device to the second semiconductor device,
[4b] wherein the ground shielded transmission path extends through the inter fan-out layer; and
[5] forming a first continuous ground shielding layer in the first semiconductor device that extends laterally over the active device and isolate a first metal layer from a second metal layer contained in the first semiconductor device, except where one or more conductive via structures couple the first and second metal layers.
The closest prior art is US 2016/0315055 (“Vogt”). Fig. 1 of Vogt will be applied to the features of claim 10 using Fig. 1 in an inverted orientation, i.e. with the solder balls facing up, just as oriented in the Instant Application’s Fig. 4. The reason for this, is that Vogt’s “active device” 28 has the contact pads 36 oriented in the same direction as those of the active device 128 of Fig. 4 of the Instant Application.
In addition, Vogt states, “FIG. 2A is a top view conceptual and schematic diagram illustrating and example of a lateral cross section (parallel to the x-y plane of FIG. 1) of an example interposer layer 58 that includes two IC dice 28A, 28B encircled in the x-y plane by an interposer portion 60.” (Vogt: ¶ 45; emphasis added). As such, the conductive pillars 22 in Fig. 1 correspond to the conductive pillars 64 in Fig. 2A. And the electrical loops 48 in Fig. 1 correspond to the electrically conductive loops 70A-70D.
With regard to claim 10, Vogt discloses, generally in Figs. 1 and 2A,
10. A method of making a semiconductor package, comprising:
[1] providing a first semiconductor device 16 [¶¶ 27-29];
[2] providing a second semiconductor device 12 [¶¶ 27-29] positioned below the first semiconductor device 16;
[3a] forming an inter fan-out layer 14(20), 58(60) [“interposer layer 14”; ¶¶ 18-19; “interposer layer 58”; ¶ 45] between the first semiconductor device 16 and the second semiconductor device 12, wherein the inter fan-out layer 14(20), 58(60) comprises
[3b] a semiconductor die 28 28A, 28B [¶¶ 19, 47, 48] containing an active device [i.e. the active devices making up the integrated circuit (IC) of the “IC die” 28, 28A, 28B, and active devices of the kind of IC die 28 listed in ¶ 34] therein,
[3c] a first ground shielding structure 48, 70B, 70C … [surrounding] … the active device [by surrounding the semiconductor die 28, 28A, 28B] so as to isolate the active device from radiation signals [¶¶ 44, 51];
[4a] forming a ground shielded transmission path [conductive pillars 22, 64 surrounded by “electrical web” 74B and/or “loop” 70D and the connected via 32, 40 and traces 34] that couples the first semiconductor device 16 to the second semiconductor device 12 [¶¶ 37, 39, 55, 58],
[4b] wherein the ground shielded transmission path extends through the inter fan-out layer 14(20), 58(60) [as shown in Fig. 1 and stated in ¶ 50]; and
[5] … [not taught] …
With regard to features [4b] of claim 1, Vogt at Fig. 1 shows that each of 48 and 22 extends through the thickness of the inter fan-out layer 14(20), and Vogt states that the electrically conductive loops 70A-70D extend through the thickness of the interposer, Vogt stating,
[0050] In some examples, interposer portion 60 also may include an electrically conductive material deposited within interposer portion 60 to create one or more electrically conductive loops 70A-70D within interposer layer 58. The electrical loops may include, for example, a continuous electrically conductive loop 70A that encircles interposer layer 58, a continuous electrically conductive loop 70B that encircles IC die 28A, a continuous electrically conductive loop 70C that encircles IC die 28B, and a continuous electrically conductive loop 70D that encircles electrical web 74B. In some examples, at least one of electrical loops 70A-70D may extend throughout the thickness of interposer layer 58 (i.e., in the z-direction) such that the at least one of electrically conductive loops 70A-70D defines a ribbon. Further, at least one of the electrically conductive loops 70A-70D may be electrically connected to a respective electrical contact 42 of one of the adjacent IC layer (e.g., IC layer 12 or 16 of FIG. 1), which may serve to electrically ground the respective electrically conductive loop.
[0051] In some examples, electrically conductive loops 70A-70D may electrically isolate and electromagnetically shield (e.g., from electromagnetic interference) the respective components that respective loops of electrically conductive loops 70A-70D encircle. …
(Vogt: ¶¶ 50-51; emphasis added)
Because “at least one” of 70A-70D may extend through the thickness, each of 70A-70D may extend through the thickness (id.). Because “at least one” of 70A-70D may be connected to a contact 42 that connects to ground, each of 70A-70D may be connected to a contact 42 that connects to ground (id.).
Even if, arguendo, having each of 70A-70D (1) extend through the thickness of the inter fan-out layer 58(60) and/or (2) connected to a contact 42 that connects to ground, was considered to not be anticipated --a point with which Examiner disagrees-- then it would have been at least obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have each of 70A-70D (1) extend through the thickness of the inter fan-out layer 58(60) and/or (2) connected to a contact 42 that connects to ground because Vogt suggests that each of 70A-70D may be.
With regard to feature [4a] of claim 1, to the extent that the conductive pillars 22 in Fig. 1 connected to the vias 32 and traces 34 are not shown to have an electrical web 74B and a grounded, electrically-conductive loop 70D around them, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include at least the grounded, electrically-conductive loop 70D and perhaps also the electrical web 74B, as shown in Fig. 2A, in order to form a grounded, electrically-isolated signal path through the interposer 58(60) between the active device 28, and (1) the vias 32 and traces 34 and (2) the second 12 semiconductor device (Vogt: ¶¶ 21-22).
Further with regard to feature [4a] of claim 1, in addition, to the extent that the conductive pillars 64 in Fig. 2A that are surrounded by the grounded conductive loop 70D, are not connected to the vias 32 and traces 34, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make said conductive pillars 64 in Fig. 2A that are surrounded by the grounded, electrically-conductive loop 70D connected to the vias 32 and traces 34, as shown in Fig. 1, in order to make a grounded, electrically-isolated signal path through the interposer 58(60) between the active device 28A, 28B, and (1) the vias 32 and traces 34 and (2) the second 12 semiconductor device (Vogt: ¶¶ 21-22).
With regard to feature [5] of claim 10,
[5] forming a first continuous ground shielding layer formed in the first semiconductor device that extends laterally over the active device and isolate a first metal layer from a second metal layer contained in the first semiconductor device, except where one or more conductive via structures couple the first and second metal layers.
While Vogt discloses the claimed “first ground shielding layer” 48, 70B, 70C extending through the interposer 14(20), 58(60) (i.e. the claimed “inter fan-out layer”), Vogt does not teach that signal path within the first 16 and second 12 semiconductor devices running through the interposer 14(20), 58(60) is also a grounded shielding path. Therefore, Vogt does not teach the claimed “first continuous ground shielding layer” having the configuration recited in feature [5]. However, Vogt states that the semiconductor devices 12, 16 can include additional metal layers and shielding layers:
[0059] Returning to FIG. 1, while IC system 10 includes three layers (interposer layer 14, and IC layers 12 and 16), systems in accordance with this disclosure may include multiple interposer layers, multiple IC layers, or both. … As yet another example, IC layers 12 and 16 (e.g., layers of the stack that do not include an interposer portion) may comprise multiple sections, instead of being a single, continuous element (as shown in the figures described herein). … In some examples, additional layers may be added to stacked IC system 10 including one or more metals layers, one or more shielding layers, or both.
(Vogt: ¶ 59; emphasis added)
Fukuoka (supra), like Vogt, teaches a 3D integrated circuit including first 31 and second 32 semiconductor devices separated by an inter fan-out layer 33, wherein signal path is formed by conductive pillars 331 through the inter fan-out layer 33, and said conductive pillars 331 are shielded by a conductive web 332 or 333 or 334 around each pillar 331. (Compare Fig. 2A of Vogt with Figs. 2, 4, and 5A of Fukuoka.) Fukuoka further teaches that the entire signal path between the first 32 and second 31 semiconductor devices, including the portion in the inter fan-out layer 33, includes a grounded shielding structure including each of (1) the claimed “first ground shield layer” within the inter fan-out layer 33, (2) the claimed “second ground shield layer” within the interconnect layers of the first semiconductor device 32 and (3) the claimed “third ground shielding layer” of claims 4-6 in the interconnect layers of the second 31 semiconductor device.
Fig. 3 of Fukuoka is reproduced below and annotated to show a signal path and ground shielding layers extending between semiconductor devices 31 and 32, including the signal path through the via 331 in the inter fan-out layer 33, said via 331 shielded by the surrounding grounded mesh 332. In this regard, Fukuoka states,
[0046] Electric potentials (hereinafter referred to as "fixed electric potentials") with constant values are provided within the first semiconductor chip 31 and the second semiconductor chip 32. A shield 332 is a noise shielding layer that is connected to a fixed electric potential (for example, the ground) of at least one of the first semiconductor chip 31 and the second semiconductor chip 32. Additionally, the shield 332 is manufactured so as to surround the respective bumps 331. …
(Fukuoka: ¶ 46; emphasis added)
[0052] In addition, if the shield 332 is connected to the fixed electric potential within the device manufacturing region 312 or 322 of either the first semiconductor chip 31 or the second semiconductor chip 32, noise mixed in signals connected via the bumps 331 can be reduced. …
[0053] In this way, in the semiconductor device 3 of the first embodiment, the shield 332 is manufactured around regions where the bumps 331 are manufactured. Accordingly, in the semiconductor device 3 of the first embodiment, even in a state where a gap between the first semiconductor chip 31 and the second semiconductor chip 32 is hollow, noise, which is mixed in the signals transmitted and received between the circuit manufactured in the first device manufacturing region 312 within the first semiconductor chip 31 and the circuit manufactured in the second device manufacturing region 322 within the second semiconductor chip 32 via the bumps 331, can be reduced, that is, noise can be shielded.
(Fukuoka: ¶ 52-53; emphasis added)
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(Annotated version of Fig. 3 of Fukuoka)
Akram, like Vogt and Fukuoka, teaches a semiconductor device having a ground shielded signal path. Akram’s Figs. 8-10 show various embodiments of a ground plane and a signal path. Fig. 8 shows the ground plane 76 between the semiconductor die 68 and the signal path 78, 82 (Akram: col. 6, line 45 to col. 7, line 38). Fig. 9, by contrast, shows the ground plane 302 above to signal path 306 (Akram: col. 7, lines 39-63). Fig. 10 is a combination of the embodiments shown in Figs. 8 and 9, therefore including ground planes 402, 404 both below 402 and above 404 the signal path 408. The ground planes 402 and 404 are horizontal “planes”, i.e. two-dimensional, horizontal planes, electrically connected together by the vertically-running portions extending between said ground planes 402 and 404. In regard to the ground planes, Akram states:
FIG. 8 is a cross-sectional view of a flip-chip semiconductor device 56, such as that shown in FIG. 3, having at least one ground plane 76 according to a first embodiment of a second aspect of the present invention. The ground plane 58 [sic; should be 76] is included among the flip-chip semiconductor device layers 60 to provide a reference basis for matching impedance, and isolate each of the signal lines 62, 64 and 66 from the electromagnetic and electrostatic fields emanating from adjacent signal lines and circuitry. … Selected portions of the ground plane 76 are then defined, for example, using well known photolithographic techniques and etched to form vias 78. This etching is performed, for example, using a solution consisting of nitric and phosphoric acids.
(Akram: col. 6, lines 45-65; emphasis added)
By placing the ground plane 302 above the electrical interconnect layer 306, the ground plane 302 isolates the signal lines 309, 310 and 312, each of substantially equal length, from circuitry on a substrate such as a printed wiring board to be coupled to the flip-chip semiconductor device 300.
(Akram: col. 7, lines 47-52; emphasis added)
FIG. 10 is a cross-sectional view of a portion of a flip-chip semiconductor device 112 [400] having at least two ground planes 116 [402] and 118 [404] according to a third embodiment of the second aspect of the present invention. This third embodiment combines the first and second embodiments in that there are two ground planes 116 [402] and 118 [404]. By placing a ground plane 116 [402] between the active surface 114 [406] of the semiconductor device 112 [400] and the electrical interconnect layer 120 [408], and a ground plane 118 [404] between the electrical interconnect layer 120 [408] and the outer surface 115 [410] of the semiconductor device 112 [400], the electrical interconnect layer 120 [408] and corresponding signal lines 122 [412], 124 [414] and 126 [416], each of substantially equal length, are isolated from both the active circuitry on the semiconductor die 128 [418] and from any circuitry on a substrate such as a printed wiring board to be coupled to the flip-chip semiconductor device 112 [400].
(Akram: col. 7, line 64 to col. 8, line 12; emphasis added)
Note that, although the reference characters recited in the paragraph describing Fig. 10 do not match those actually shown in the Fig. 10, the description, including that which is shown in Figs. 8 and 9, makes clear that the reference characters could only be interpreted as shown in square brackets, above.
Akram further shows that the ground planes 402 and 404 have openings for allowing the vias (vertically-running portions) of the “signal lines 122 [412], 124 [414] and 126 [416]” to pass through.
Still further, Akram states that the ground shielded circuit applies to multi-level interconnect, wherein the ground plane can be formed between each layer of interconnect, stating in this regard,
It is also contemplated and will be understood by one of ordinary skill in the art that while only a single electrical interconnect layer has been shown and described with respect to each of the embodiments herein, two or more electrical interconnect layers may be formed, each separated from other conductive layers by a dielectric layer or two dielectric layers and a ground plane using similar methods well known in the art.
(Akram: col. 8, lines 21-28; emphasis added)
Thus, Akram expressly teaches including plural metal layers of interconnect each separated from the other by ground shield plane and therefore teaches the concept of the Instant Application as shown in Fig. 4. In other words, the claimed concept of isolating each of the metal interconnect layers from the others by a continuous ground shielding structure is shown in Fig. 10 of Akram.
In addition, Akram’s Fig. 10 shows that (1) the ground planes 402, 404 extend horizontally in via layer of the signal path 412, 414, 416, i.e. the vertically-running portion of the signal paths 412, 414, 416, and (2) the horizontally-running portion of the signal paths 412, 414, 416, are formed in the via layer connecting the ground planes 402 and 404.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to extend the ground shielding layer 46, 70F, 74B in the inter fan-out layer 14(20), 58(60) of Vogt to include a continuous ground shielding structure surrounding each of the signal paths 32, 34, 40 within the first 16 and second 12 semiconductor devices of Vogt, configured as taught in Akram, and electrically connected to the grounded shielding structures 70A-70D within the interposer 58(60) (i.e. the claimed “inter fan-out layer”) of Vogt, in order to form continuous ground shielding path surrounding the entire length of the signal paths 32, 34, 40 between each of the first 16 and second 12 semiconductor devices, as well as the active device 28A, 28B. The motivation would be to reduce noise in the signal path by providing shielding along the entire length of the path, as taught in Akram and Fukuoka (supra). As such, Fukuoka and Akram may be seen as an improvement to Vogt in this regard. (See MPEP 2143.)
There is a reasonable expectation of success in applying the grounded signal path of Fukuoka/Akram to Vogt since Fukuoka already includes a portion of the wires 314, 324 connected to the shield layer 332 that form a portion of the overall ground shield structure 314/332/324.
With regard to feature [3c] of claim 10, Vogt does not teach that the claimed “first ground shield structure” 48, 70B, 70C is within the semiconductor die 28, 28A, 28B, itself. It is, however, known to include a ground shield within a semiconductor device, such as taught in any of US 2010/0078779 (“Barth”), US 2016/0111376 (“Seo”), and US 2010/0140749 (“Kuo”), it is not clear that one having ordinary skill in the art would further make the change to Vogt given that Vogt uses a ground shield formed outside of the semiconductor die 28, 28A, 28B.
As such the prior art does not reasonably teach or suggest—in the context of claim 10—the that the first ground shield structure is “within the semiconductor die”. Claims 11-15 would be allowable at least for including the same limitation by depending from claim 10.
C. Claim 16
Claim 16 reads,
16. A method of making a semiconductor package, comprising:
[1] providing a first semiconductor device comprising a first metal layer and a second metal layer formed over the first metal layer;
[2] providing a second semiconductor device positioned below the first semiconductor device;
[3a] forming an inter fan-out layer between the first semiconductor device and the second semiconductor device and below the first metal layer, wherein the inter fan-out layer comprises
[3b] a semiconductor die containing an active device therein and
[3c] first ground shielding structure within the semiconductor die and disposed about the active device so as to isolate the active device from radiation signals;
[4] forming a ground shielded transmission path that couples the first semiconductor device to the second semiconductor device; and
[5a] forming a continuous ground shielding layer extending laterally over the active device so as to isolate the first and second metal layers from each other except where one or more first conductive via structures couple the first and second metal layers,
[5b] wherein the continuous ground shielding layer is conductively coupled to the first ground shielding structure and ground.
A comparison with claim 10 shows that Vogt in view of Fukuoka and Akram teaches each of the features of claim 16 except that the first ground shielding structure is “within the semiconductor die”.
As such the prior art does not reasonably teach or suggest—in the context of claim 16—the that the first ground shielding structure is “within the semiconductor die”.
Claims 17-20 would be allowable at least for including the same limitation by depending from claim 16.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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