DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (US 2017/0110456) (hereafter Jeon).
Regarding claim 1, Jeon discloses a device comprising:
a plurality of gate stacks (151a and 151b in Fig. 32, paragraph 0074) over a substrate (101 and F1-F3 in Fig. 32, paragraph 0056), the plurality of gate stacks (151a and 151b in Fig. 32) forming first strip patterns (151a and 151b in Fig. 32) extending along a first direction (Y1 direction in Fig. 32) from a top view;
a plurality of shallow trench isolation (STI) regions 110 (Fig. 32, paragraph 0146) inlaid in the substrate (101 and F1-F3 in Fig. 32) from a cross-sectional view (see Fig. 32, wherein portion of 110 formed between F1 and F2), the plurality of STI regions 110 (Fig. 32) forming second strip patterns 110 (Fig. 32) extending parallel with the first strip patterns (151a and 151b in Fig. 32) of the plurality of gate stacks along the first direction (Y1 direction in Fig. 32) from the top view, the plurality of STI regions 110 (Fig. 32) being formed of a single continuous material that spans the plurality of the gate stacks (151a and 151b in Fig. 32) from the cross-sectional view (see Fig. 32, wherein potion of 110 formed between 151a and 151b); and
source/drain regions (121, 123, and 125 in Fig. 32, paragraph 0073) alternately arranged with the plurality of gate stacks (151a and 151b in Fig. 32).
Regarding claim 2, Jeon (utilized different elements for a substrate and a plurality of shallow trench isolation (STI) regions as applied in claim 1 in the above) discloses a device comprising:
a plurality of gate stacks (151a and 151b in Fig. 32, paragraph 0074) over a substrate (101, 110, 115, and F1-F3 in Fig. 32, paragraph 0056), the plurality of gate stacks (151a and 151b in Fig. 32) forming first strip patterns (151a and 151b in Fig. 32) extending along a first direction (Y1 direction in Fig. 32) from a top view;
a plurality of shallow trench isolation (STI) regions (131 and 132 in Fig. 33, paragraph 0130) inlaid in the substrate (101 and F2 in Fig. 33 and 115 (element number is not shown in Fig. 33 but see Fig. 32)) from a cross-sectional view, the plurality of STI regions (131 and 132 in Fig. 33) forming second strip patterns (see 131 in Fig. 8) extending parallel with the first strip patterns (151a and 151b in Fig. 32) of the plurality of gate stacks along the first direction (Y1 direction in Fig. 32) from the top view, the plurality of STI regions (131 and 132 in Fig. 33) being formed of a single continuous material (see paragraph 0078, wherein “oxide layer”; and paragraph 0179, wherein “oxide”) that spans the plurality of the gate stacks (151a and 151b in Fig. 32) from the cross-sectional view;
source/drain regions (121, 123, and 125 in Fig. 32, paragraph 0073) alternately arranged with the plurality of gate stacks (151a and 151b in Fig. 32); and
wherein the single continuous material (131 and 132 in Fig. 33) of the plurality of STI regions (131 and 132 in Fig. 33) directly contacts a metal layer (MG2 in Fig. 33, paragraph 0126) of at least one of the plurality of gate stacks (151a and 151b in Fig. 33) from the cross-sectional view.
Regarding claim 4, Jeon further discloses the device of claim 1, wherein each source/drain region of the source/drain regions 123 (Fig. 34) has a cross-sectional pattern that is symmetrical about a plane of symmetry.
Regarding claim 5, Jeon (utilized different elements for a plurality of shallow trench isolation (STI) regions as applied in claim 1 in the above) discloses a device comprising:
a plurality of gate stacks (151a and 151b in Fig. 32, paragraph 0074) over a substrate (101 and F1-F3 in Fig. 32, paragraph 0056), the plurality of gate stacks (151a and 151b in Fig. 32) forming first strip patterns (151a and 151b in Fig. 32) extending along a first direction (Y1 direction in Fig. 32) from a top view;
a plurality of shallow trench isolation (STI) regions 175 (Fig. 33, paragraph 0146) inlaid in the substrate (101 and F2 in Fig. 33) from a cross-sectional view, the plurality of STI regions 175 (Fig. 32) forming second strip patterns 110 (Fig. 32) extending parallel with the first strip patterns (151a and 151b in Fig. 32) of the plurality of gate stacks along the first direction (Y1 direction in Fig. 32) from the top view, the plurality of STI regions 175 (Fig. 33) being formed of a single continuous material that spans the plurality of the gate stacks (151a and 151b in Fig. 32) from the cross-sectional view;
source/drain regions (121, 123, and 125 in Fig. 32, paragraph 0073) alternately arranged with the plurality of gate stacks (151a and 151b in Fig. 32); and
wherein from the top view, the first strip patterns (151a and 151b in Fig. 32) of the plurality of gate stacks have a same width as the second strip patterns 175 (Fig. 32) of the plurality of STI regions.
Regarding claim 6, Jeon further discloses the device of claim 1, wherein the source/drain regions (121, 123, and 125 in Fig. 32, paragraph 0074, wherein “SiGe”) are formed of silicon germanium.
Regarding claim 7, Jeon further discloses the device of claim 1, wherein each of the source/drain regions (121, 123, and 125 in Fig. 32) has a hexagonal cross-section.
Regarding claim 8, Jeon discloses a device comprising:
an N-type field-effect-transistor (NFET) gate 151a (Fig. 32, paragraph 0074; and see paragraph 0167, wherein “the semiconductor device according to FIGS. 32 and 33 may be formed in the first region I and/or the second region II of FIGS. 14A to 14D”; see “I” region in Fig. 14B; and see paragraph 0100, wherein “the first region I is a region in which an NMOS transistor is formed, and the second region II is a region in which a PMOS transistor is formed”) over a substrate (101 and F1-F3 in Fig. 32, paragraph 0056) and forming a first strip pattern 151a (Fig. 32) from a top view;
a P-type field-effect-transistor (PFET) gate 151b (Fig. 32, paragraph 0074) over the substrate (101 and F1-F3 in Fig. 32) and forming a second strip pattern 151b (Fig. 32) from the top view; and
an STI region 110 (Fig. 32, paragraph 0061) extending into the substrate (101 and F1-F3 in Fig. 32) from a cross-sectional view (see Fig. 32, wherein portion of 110 formed between F1 and F2), the STI region 110 (Fig. 32) forming a third strip pattern 110 (Fig. 32) interposing the first strip pattern 151a (Fig. 32) of the NFET gate and the second strip pattern 151b (Fig. 32) of the PFET gate from the top view, the STI region 110 (Fig. 32) being formed of a single continuous material that covers both the NFET gate 151a (Fig. 32) and the PFET gate 151b (Fig. 32) from the cross-sectional view (see Fig. 32, wherein 110 covers the bottom surfaces of 151a and 151b).
Regarding claim 9, Jeon (utilized different elements for a substrate and a plurality of shallow trench isolation (STI) regions as applied in claim 8 in the above) discloses a device comprising:
an N-type field-effect-transistor (NFET) gate 151a (Fig. 32, paragraph 0074; and see paragraph 0167, wherein “the semiconductor device according to FIGS. 32 and 33 may be formed in the first region I and/or the second region II of FIGS. 14A to 14D”; see “I” region in Fig. 14B; and see paragraph 0100, wherein “the first region I is a region in which an NMOS transistor is formed, and the second region II is a region in which a PMOS transistor is formed”) over a substrate (101, 110, 115, and F1-F3 in Fig. 32, paragraph 0056) and forming a first strip pattern 151a (Fig. 32) from a top view;
a P-type field-effect-transistor (PFET) gate 151b (Fig. 32, paragraph 0074) over the substrate (101, 110, 115, and F1-F3 in Fig. 32, paragraph 0056) and forming a second strip pattern 151b (Fig. 32) from the top view;
an STI region (131 and 132 in Fig. 33, paragraph 0130) extending into the substrate (101 and F2 in Fig. 33 and 115 (element number is not shown in Fig. 33 but see Fig. 32)) from a cross-sectional view, the STI region (131 and 132 in Fig. 33) forming a third strip pattern (see 131 in Fig. 8) interposing the first strip pattern 151a (Fig. 32) of the NFET gate and the second strip pattern 151b (Fig. 32) of the PFET gate from the top view, the STI region (131 and 132 in Fig. 33) being formed of a single continuous material (see paragraph 0078, wherein “oxide layer”; and paragraph 0179, wherein “oxide”) that covers both the NFET gate 151a (Fig. 32) and the PFET gate 151b (Fig. 32) from the cross-sectional view; and
wherein the single continuous material (131 and 132 in Fig. 33) of the STI region is in contact with a metal layer (MG2 in Fig. 33, paragraph 0126) of the NFET gate 151a (Fig. 33).
Regarding claim 10, Jeon (utilized different elements for a substrate and a plurality of shallow trench isolation (STI) regions as applied in claim 8 in the above) discloses a device comprising:
an N-type field-effect-transistor (NFET) gate 151a (Fig. 32, paragraph 0074; and see paragraph 0167, wherein “the semiconductor device according to FIGS. 32 and 33 may be formed in the first region I and/or the second region II of FIGS. 14A to 14D”; see “I” region in Fig. 14B; and see paragraph 0100, wherein “the first region I is a region in which an NMOS transistor is formed, and the second region II is a region in which a PMOS transistor is formed”) over a substrate (101, 110, 115, and F1-F3 in Fig. 32, paragraph 0056) and forming a first strip pattern 151a (Fig. 32) from a top view;
a P-type field-effect-transistor (PFET) gate 151b (Fig. 32, paragraph 0074) over the substrate (101, 110, 115, and F1-F3 in Fig. 32, paragraph 0056) and forming a second strip pattern 151b (Fig. 32) from the top view;
an STI region (131 and 132 in Fig. 33, paragraph 0130) extending into the substrate (101 and F2 in Fig. 33 and 115 (element number is not shown in Fig. 33 but see Fig. 32)) from a cross-sectional view, the STI region (131 and 132 in Fig. 33) forming a third strip pattern (see 131 in Fig. 8) interposing the first strip pattern 151a (Fig. 32) of the NFET gate and the second strip pattern 151b (Fig. 32) of the PFET gate from the top view, the STI region (131 and 132 in Fig. 33) being formed of a single continuous material (see paragraph 0078, wherein “oxide layer”; and paragraph 0179, wherein “oxide”) that covers both the NFET gate 151a (Fig. 32) and the PFET gate 151b (Fig. 32) from the cross-sectional view; and
wherein the single continuous material (131 and 132 in Fig. 33) of the STI region is in contact with a metal layer (MG2 in Fig. 33, paragraph 0126) of the PFET gate 151b (Fig. 33).
Regarding claim 11, Jeon further discloses the device of claim 8, wherein from the top view, the third strip pattern 110 (Fig. 32) of the STI region has a longitudinal axis parallel with a longitudinal axis of the first strip pattern 151a (Fig. 32) of the NFET gate.
Regarding claim 12, Jeon further discloses the device of claim 8, wherein from the top view, the third strip pattern 110 (Fig. 32) of the STI region has a longitudinal axis parallel with a longitudinal axis of the second strip pattern 151b (Fig. 32) of the PFET gate.
Regarding claim 13, Jeon discloses a device comprising:
a first transistor (transistor with 151a in Fig. 32, paragraph 0074,wherein “PMOS transistor”) over a substrate (101 and F1-F3 in Fig. 32, paragraph 0056), the first transistor (transistor with 151a in Fig. 32) comprising a first gate structure 151a (Fig. 32, paragraph 0074) and first epitaxial source/drain regions (121, 123, and 125 of 151a in Fig. 32, paragraph 0074) at opposite sides of the first gate structure 151a (Fig. 32);
a second transistor (transistor with 151b in Fig. 32, paragraph 0074,wherein “PMOS transistor”) over the substrate (101 and F1-F3 in Fig. 32), the second transistor (transistor with 151b in Fig. 32) comprising a second gate structure 151b (Fig. 32, paragraph 0074) and second epitaxial source/drain regions (121, 123, and 125 of 151b in Fig. 32, paragraph 0074) at opposite sides of the second gate structure 151b (Fig. 32); and
a dielectric structure (110 (Fig. 32) , 115 (Fig. 32), 131 (Fig. 33), and 132 (Fig. 33)) comprising:
a lateral portion (131 and 132 in Fig. 33) laterally extending over the first gate structure 151a (Fig. 33) of the first transistor and the second gate structure 151b (Fig. 33) of the second transistor; and
a vertical portion (110 and 115 in Fig. 32) vertically extending from the lateral portion into the substrate (101 and F1-F3 in Fig. 32), the vertical portion (110 and 115 in Fig. 32) being positioned between one of the first epitaxial source/drain regions (121, 123, and 125 of 151a in Fig. 32) and one of the second epitaxial source/drain regions (121, 123, and 125 of 151b in Fig. 32), the lateral portion (131 and 132 in Fig. 33) and the vertical portion (110 and 115 in Fig. 32) being formed a single continuous dielectric material that extends across the first 151a (Fig. 32) and second gate structures 151b (Fig. 32).
Regarding claim 14, Jeon further discloses the device of claim 13, wherein the single continuous dielectric material (110 (Fig. 32) , 115 (Fig. 32), 131 (Fig. 33), and 132 (Fig. 33)) interfaces with a metal material (MG2 in Fig. 33, paragraph 0126) of the first 151a (Fig. 33) and second gate structures 151b (Fig. 33).
Regarding claim 16, Jeon further discloses the device of claim 13, wherein the first transistor (transistor with 151a in Fig. 32, paragraph 0074,wherein “PMOS transistor”) and the second transistor (transistor with 151b in Fig. 32, paragraph 0074,wherein “PMOS transistor”) are of a same conductivity type.
Regarding claim 17, Jeon further discloses the device of claim 13, wherein the vertical portion of the dielectric structure (110 (Fig. 32) , 115 (Fig. 32), 131 (Fig. 33), and 132 (Fig. 33)) has a bottom surface lower than a bottom surface of one of the first epitaxial source/drain regions (121, 123, and 125 of 151a in Fig. 32).
Regarding claim 18, Jeon further discloses the device of claim 13, wherein in a top view, the vertical portion (110 and 115 in Fig. 32) of the dielectric structure has a strip pattern 115 (Fig. 32) extending parallel with the first gate structure 151a (Fig. 32).
Regarding claim 19, Jeon further discloses the device of claim 13, wherein the vertical portion (110 and 115 in Fig. 32) of the dielectric structure has a non-linear sidewall.
Regarding claim 20, Jeon further discloses the device of claim 13, wherein a sidewall of the vertical portion (110 and 115 in Fig. 32) of the dielectric structure exhibits a change in slope (see outer sidewall of 115 in Fig. 32) at a top surface of the substrate (101 and F1-F3 in Fig. 32).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon as applied to claims 1 and 13 above, and further in view of Yeong et al. (US 2018/0175175) (hereafter Yeong).
Regarding claim 3, Jeon discloses the device of claim 1, however Jeon does not disclose the single continuous material of the plurality of STI regions is phosphosilicate glass.
Yeong discloses the single continuous material of the plurality of STI regions 420 (Fig. 5, paragraph 0039, wherein “phosphosilicate glass (PSG) liner layer”) is phosphosilicate glass.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jeon to form the single continuous material of the plurality of STI regions is phosphosilicate glass, as taught by Yeong, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 15, Jeon discloses the device of claim 13, however Jeon does not disclose the single continuous dielectric material is phosphosilicate glass.
Yeong discloses the single continuous dielectric material 420 (Fig. 5, paragraph 0039, wherein “phosphosilicate glass (PSG) liner layer”) is phosphosilicate glass.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jeon to form the single continuous dielectric material is phosphosilicate glass, as taught by Yeong, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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