DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 4, 9, 11 and 17 are objected to because of the following informalities: regarding claims 1, 11 and 17, line 9 of each, replace the phrase “electrically to the contact” with --electrically connected to the contact-- for proper grammar; regarding claim 4, line 2, replace “comprising” with --comprises-- for proper grammar; regarding claim 9, in lines 1-2, replace the phrase “wherein contact comprise an lower metal portion” with --wherein the contact comprises a lower metal portion-- for proper grammatical construction. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 10-12, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al (US Patent Application Publication 2020/0043721), henceforth Liou ‘721, in view of Flachowsky et al (US Patent Application Publication 2013/0175545) and Liou et al (US Patent Application Publication 2019/0096820), henceforth Liou ‘820.
Regarding claim 1, Liou ‘721 discloses a semiconductor device, comprising:
a gate 64 disposed on a substrate 50 [see Fig. 1A; see also paragraph 0012];
a source/drain region 54 disposed in the substrate and aside the gate [see Fig. 1A; see also paragraph 0012]
an insulating layer 76, 78 disposed over the substrate [see Fig. 1A; see also paragraph 0012];
a contact 74 penetrating through the insulating layer and electrically connected to a source/drain region [see Fig. 1A; see also paragraph 0012];
a zeroth dielectric layer 20 disposed on the insulating layer [see Fig. 1A; see also paragraph 0013];
a zeroth metal layer 88 penetrating through the zeroth dielectric layer and electrically connected to the contact [see Fig. 1A; see also paragraph 0013];
a first dielectric layer 100 disposed on the zeroth dielectric layer [see Fig. 1A; see also paragraph 0013]; and
a first metal layer 104, 108 penetrating through the first dielectric layer and electrically connected to the zeroth metal layer [see Fig. 1A; see also paragraph 0013].
Liou ‘721 do not disclose wherein the source/drain region is a strained layer, nor wherein a dielectric constant of the zeroth dielectric layer is higher than a dielectric constant of the first dielectric layer, and a hardness of the zeroth dielectric layer is greater than a hardness of the first dielectric layer. One such as Flachowsky et al disclose a gate 28 disposed on a substrate 21; and a source/drain region 22, 24 comprising a strained layer [see Fig. 1; see also paragraph 0016]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the source/drain regions of Liou ‘721 from a strained layer, as taught by Flachowsky et al, in order to induce strain in the channel region, which is known to improve transistor performance.
Furthermore, one such as Liou ‘820 disclose a substantially similar semiconductor device, including formation of successive dielectric layers analogous to a zeroth dielectric layer 110 disposed on an insulating layer 104 [see Fig. 1; see also paragraph 0023]; a zeroth metal layer 112 penetrating through the zeroth dielectric layer and electrically connected to the contact [see Fig. 1; see also paragraph 0023]; a first dielectric layer 118 disposed on the zeroth dielectric layer [see Fig. 1; see also paragraph 0023]. Liou ‘820 further teach that a dielectric constant of the zeroth dielectric layer 110 is higher than a dielectric constant of the first dielectric layer 118 [see paragraph 0030], and a hardness of the zeroth dielectric layer 110 is greater than the hardness of the first dielectric layer 118 [see paragraph 0030]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the dielectric layers to have the claimed relative dielectric constants and hardnesses because Liou ‘820 disclose that the hardnesses and dielectric constants compensate for the pitches of the interconnects formed therein, and increased material hardness and dielectric constant benefits a narrower pitch of interconnect, which Liou ‘721 disclose to be formed in the zeroth dielectric layer, because a harder dielectric with a higher dielectric constant provides mechanical support for the narrower openings and reduces dielectric layer bending during fabrication [see paragraph 0027].
Regarding claim 2, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 1. Furthermore to the dielectric constant of the zeroth dielectric layer, Liou ‘820 disclose wherein a dielectric constant of the zeroth dielectric layer is less than 3.2 and greater than 3.0 [see paragraph 0024, wherein the layer that is the equivalent of the zeroth dielectric layer is disclosed to be preferably in the claimed range].
Regarding claim 4, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 1. Furthermore, Liou ‘721 disclose wherein the first dielectric layer comprises a silicon-containing linear compound, and wherein the silicon-containing linear compound comprises diethoxymethylsilane (DEMS), dimethoxydimethylsilane (DMDMOS) or a derivative thereof [see paragraph 0038].
Regarding claim 5, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 1. Furthermore to the relative dielectric constants, Liou ‘820 disclose wherein the dielectric constant of the zeroth dielectric layer is from about 3.10 to 3.19 [see paragraph 0024, wherein the disclosed values substantially overlap the claim], and the dielectric constant of the first dielectric layer is from about 3.06 to 3.14 [see paragraph 0027, wherein the disclosed values substantially overlap the claim].
Regarding claim 6, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 1. Furthermore, Liou ‘721 disclose wherein each of the zeroth dielectric layer and the first dielectric layer comprises SiOC, SiOCH or a combination thereof [see paragraph 0044].
Regarding claim 10, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 1. Furthermore, Liou ‘721 disclose comprising an etching stop layer 21 between the zeroth dielectric layer and the insulating layer, wherein the etching stop layer comprises SiCN, AlN, Al2O3, TaO, LaO or a combination thereof [see paragraph 0036].
Regarding claim 11, Liou ‘721 discloses a semiconductor device, comprising:
a gate 64 disposed on a substrate 50 [see Fig. 1A; see also paragraph 0012];
a source/drain region 54 disposed in the substrate and aside the gate [see Fig. 1A; see also paragraph 0012]
an insulating layer 76, 78 disposed over the substrate [see Fig. 1A; see also paragraph 0012];
a contact 74 penetrating through the insulating layer and electrically connected to a source/drain region [see Fig. 1A; see also paragraph 0012];
a zeroth dielectric layer 20 disposed on the insulating layer [see Fig. 1A; see also paragraph 0013];
a zeroth metal layer 88 penetrating through the zeroth dielectric layer and electrically connected to the contact [see Fig. 1A; see also paragraph 0013];
an etching stop layer 21 between the zeroth dielectric layer and the insulating layer and around the zeroth dielectric layer [see Fig. 1A; see also paragraph 0036];
a first dielectric layer 100 disposed on the zeroth dielectric layer [see Fig. 1A; see also paragraph 0013]; and
a first metal layer 104, 108 penetrating through the first dielectric layer and electrically connected to the zeroth metal layer [see Fig. 1A; see also paragraph 0013].
Liou ‘721 do not disclose wherein the source/drain region is a strained layer, nor wherein a dielectric constant of the zeroth dielectric layer is higher than a dielectric constant of the first dielectric layer, and a hardness of the zeroth dielectric layer is greater than a hardness of the first dielectric layer. One such as Flachowsky et al disclose a gate 28 disposed on a substrate 21; and a source/drain region 22, 24 comprising a strained layer [see Fig. 1; see also paragraph 0016]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the source/drain regions of Liou ‘721 from a strained layer, as taught by Flachowsky et al, in order to induce strain in the channel region, which is known to improve transistor performance.
Furthermore, one such as Liou ‘820 disclose a substantially similar semiconductor device, including formation of successive dielectric layers analogous to a zeroth dielectric layer 110 disposed on an insulating layer 104 [see Fig. 1; see also paragraph 0023]; a zeroth metal layer 112 penetrating through the zeroth dielectric layer and electrically connected to the contact [see Fig. 1; see also paragraph 0023]; a first dielectric layer 118 disposed on the zeroth dielectric layer [see Fig. 1; see also paragraph 0023]. Liou ‘820 further teach that a dielectric constant of the zeroth dielectric layer 110 is higher than a dielectric constant of the first dielectric layer 118 [see paragraph 0030], and a hardness of the zeroth dielectric layer 110 is greater than the hardness of the first dielectric layer 118 [see paragraph 0030]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the dielectric layers to have the claimed relative dielectric constants and hardnesses because Liou ‘820 disclose that the hardnesses and dielectric constants compensate for the pitches of the interconnects formed therein, and increased material hardness and dielectric constant benefits a narrower pitch of interconnect, which Liou ‘721 disclose to be formed in the zeroth dielectric layer, because a harder dielectric with a higher dielectric constant provides mechanical support for the narrower openings and reduces dielectric layer bending during fabrication [see paragraph 0027].
Regarding claim 12, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 11. Furthermore to the dielectric constant of the zeroth dielectric layer, Liou ‘820 disclose wherein a dielectric constant of the zeroth dielectric layer is less than 3.2 and greater than 3.0 [see paragraph 0024, wherein the layer that is the equivalent of the zeroth dielectric layer is disclosed to be preferably in the claimed range].
Regarding claim 14, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 11. Furthermore to the relative dielectric constants, Liou ‘820 disclose wherein the dielectric constant of the zeroth dielectric layer is from about 3.10 to 3.19 [see paragraph 0024, wherein the disclosed values substantially overlap the claim], and the dielectric constant of the first dielectric layer is from about 3.06 to 3.14 [see paragraph 0027, wherein the disclosed values substantially overlap the claim].
Regarding claim 15, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor device of claim 11. Furthermore, Liou ‘721 disclose wherein each of the zeroth dielectric layer and the first dielectric layer comprises SiOC, SiOCH or a combination thereof [see paragraph 0044].
Claims 3, 13 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al (US Patent Application Publication 2020/0043721), henceforth Liou ‘721, in view of Flachowsky et al (US Patent Application Publication 2013/0175545) and Liou et al (US Patent Application Publication 2019/0096820), henceforth Liou ‘820 as applied to claim 1 above, and further in view of Vrtis et al (US Patent Application Publication 2015/0364321).
Regarding claims 3 and 13, the prior art of Liou ‘721, Flachowsky et al and Liou ‘820 disclose the semiconductor devices of claims 1 and 11. None of Liou ‘721, Flachowsky et al and Liou ‘820 disclose with specificity wherein the zeroth dielectric layer comprises a silicon-containing heterocyclic compound, and the silicon-containing heterocyclic compound is represented by one of the formulae (I) and (II):
PNG
media_image1.png
190
174
media_image1.png
Greyscale
wherein R is CxH2x+1, and x is an integer from 1 to 6.
One such as Vrtis et al disclose the use of silicon-containing heterocyclic compounds of formulae (I) and (II) for forming porous, low-k dielectric films for use as interlayer dielectrics [see paragraph 0009, 0024 and 0033, wherein formula (I), wherein R is CH3 (x=1) or C2H5 (x=2), is disclosed, and wherein formula (II), wherein R is CH3 (x=1) or C2H5 (x=2), is disclosed]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the zeroth dielectric layer using the compounds disclosed by Vrtis et al because these compounds form dielectric layers having tunable hardness and low dielectric constants, and the compounds themselves beneficially have lower molecular weight relative to other structure-forming precursors such as bridged precursors [see paragraph 0009].
Regarding claim 17, Liou ‘721 discloses a semiconductor device, comprising:
a gate 64 disposed on a substrate 50 [see Fig. 1A; see also paragraph 0012];
a source/drain region 54 disposed in the substrate and aside the gate [see Fig. 1A; see also paragraph 0012]
an insulating layer 76, 78 disposed over the substrate [see Fig. 1A; see also paragraph 0012];
a contact 74 penetrating through the insulating layer and electrically connected to a source/drain region [see Fig. 1A; see also paragraph 0012];
a zeroth dielectric layer 20 disposed on the insulating layer [see Fig. 1A; see also paragraph 0013];
a zeroth metal layer 88 penetrating through the zeroth dielectric layer and electrically connected to the contact [see Fig. 1A; see also paragraph 0013];
a first dielectric layer 100 disposed on the zeroth dielectric layer [see Fig. 1A; see also paragraph 0013]; and
a first metal layer 104, 108 penetrating through the first dielectric layer and electrically connected to the zeroth metal layer [see Fig. 1A; see also paragraph 0013], and
wherein the first dielectric layer comprises a silicon-containing linear compound [see paragraph 0038].
Liou ‘721 do not disclose wherein the source/drain region is a strained layer, nor wherein a dielectric constant of the zeroth dielectric layer is higher than a dielectric constant of the first dielectric layer, and a hardness of the zeroth dielectric layer is greater than a hardness of the first dielectric layer. One such as Flachowsky et al disclose a gate 28 disposed on a substrate 21; and a source/drain region 22, 24 comprising a strained layer [see Fig. 1; see also paragraph 0016]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the source/drain regions of Liou ‘721 from a strained layer, as taught by Flachowsky et al, in order to induce strain in the channel region, which is known to improve transistor performance.
Furthermore, one such as Liou ‘820 disclose a substantially similar semiconductor device, including formation of successive dielectric layers analogous to a zeroth dielectric layer 110 disposed on an insulating layer 104 [see Fig. 1; see also paragraph 0023]; a zeroth metal layer 112 penetrating through the zeroth dielectric layer and electrically connected to the contact [see Fig. 1; see also paragraph 0023]; a first dielectric layer 118 disposed on the zeroth dielectric layer [see Fig. 1; see also paragraph 0023]. Liou ‘820 further teach that a dielectric constant of the zeroth dielectric layer 110 is higher than a dielectric constant of the first dielectric layer 118 [see paragraph 0030], and a hardness of the zeroth dielectric layer 110 is greater than the hardness of the first dielectric layer 118 [see paragraph 0030]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the dielectric layers to have the claimed relative dielectric constants and hardnesses because Liou ‘820 disclose that the hardnesses and dielectric constants compensate for the pitches of the interconnects formed therein, and increased material hardness and dielectric constant benefits a narrower pitch of interconnect, which Liou ‘721 disclose to be formed in the zeroth dielectric layer, because a harder dielectric with a higher dielectric constant provides mechanical support for the narrower openings and reduces dielectric layer bending during fabrication [see paragraph 0027].
Finally, none of Liou ‘721, Flachowsky et al and Liou ‘820 disclose with specificity wherein the zeroth dielectric layer comprises a silicon-containing heterocyclic compound, and the silicon-containing heterocyclic compound is represented by one of the formulae (I) and (II):
PNG
media_image1.png
190
174
media_image1.png
Greyscale
wherein R is CxH2x+1, and x is an integer from 1 to 6.
One such as Vrtis et al disclose the use of silicon-containing heterocyclic compounds of formulae (I) and (II) for forming porous, low-k dielectric films for use as interlayer dielectrics [see paragraph 0009, 0024 and 0033, wherein formula (I), wherein R is CH3 (x=1) or C2H5 (x=2), is disclosed, and wherein formula (II), wherein R is CH3 (x=1) or C2H5 (x=2), is disclosed]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the zeroth dielectric layer using the compounds disclosed by Vrtis et al because these compounds form dielectric layers having tunable hardness and low dielectric constants, and the compounds themselves beneficially have lower molecular weight relative to other structure-forming precursors such as bridged precursors [see paragraph 0009].
Regarding claim 18, the prior art of Liou ‘721, Flachowsky et al, Liou ‘820 and Vrtis et al disclose the semiconductor device of claim 17. Furthermore to the dielectric constant of the zeroth dielectric layer, Liou ‘820 disclose wherein a dielectric constant of the zeroth dielectric layer is less than 3.2 and greater than 3.0 [see paragraph 0024, wherein the layer that is the equivalent of the zeroth dielectric layer is disclosed to be preferably in the claimed range].
Regarding claim 19, the prior art of Liou ‘721, Flachowsky et al, Liou ‘820 and Vrtis et al disclose the semiconductor device of claim 17. Furthermore to the silicon-containing heterocyclic compound, Vrtis et al disclose the use of silicon-containing heterocyclic compounds of formulae (I) and (II) for forming porous, low-k dielectric films for use as interlayer dielectrics [see paragraph 0009, 0024 and 0033, wherein formula (I), wherein R is CH3 (x=1) or C2H5 (x=2), is disclosed, and wherein formula (II), wherein R is CH3 (x=1) or C2H5 (x=2), is disclosed].
Regarding claim 20, the prior art of Liou ‘721, Flachowsky et al, Liou ‘820 and Vrtis et al disclose the semiconductor device of claim 17. Furthermore, Liou ‘721 disclose wherein the silicon-containing linear compound comprises diethoxymethylsilane (DEMS), dimethoxydimethylsilane (DMDMOS) or a derivative thereof [see paragraph 0038].
Allowable Subject Matter
Claims 7-9 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claims 7 and 16, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, wherein the first dielectric layer comprises a porous dielectric material while the zeroth dielectric layer is free of a porous dielectric material.
Regarding dependent claim 8, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, wherein the zeroth dielectric layer comprises an oxygen-rich dielectric layer and a carbon-rich dielectric layer disposed over and in direct contact with the oxygen-rich layer.
Regarding dependent claim 9, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, wherein the width of the lower metal portion is greater than a width of the upper metal portion.
Conclusion
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/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899
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