Prosecution Insights
Last updated: October 01, 2026
Application No. 18/766,674

PACKAGE STRUCTURE

Non-Final OA §102
Filed
Jul 09, 2024
Priority
May 19, 2020 — continuation of 11/282,825 +1 more
Examiner
ULLAH, ELIAS
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
729 granted / 858 resolved
+25.0% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
867
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
35.6%
-4.4% vs TC avg
§102
53.6%
+13.6% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 858 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Soyano, US 2016/0035646. Regarding claim 1, Soyano shows a structure, comprising: a wiring substrate (substrate 11-2C in FIG. 9a); a device (chip 3 and [0058]) disposed on and electrically connected to the wiring substrate (substrate 11-2c) ; an insulating encapsulation (sealing 9) disposed on the wiring substrate and laterally encapsulating the device (chip 3); a lid disposed ( case 72 as shown in FIG. 21) on the device and the insulating encapsulation; a reinforcement structure ( feed block 4 and [0060]) embedded in the insulating encapsulation ( sealing 9); and fastening elements (lead pins 7) penetrating through the lid ( case 72), wherein the lid is fastened to the reinforcement structure through the fastening elements (see FIG. 22 with respect to FIG. 9a). Regarding claim 2, Soyano shows a structure, further comprising: an adhesive ([0139]) disposed between the insulating encapsulation (sealing 9) and the lid (lid 72); and a thermal interface material disposed between the device and the lid (see FIG. 9a with respect to FIG. 22). Regarding claim 3, Soyano shows a structure, further comprising: a first metallic layer (element between radiation block 6 and chip 3 in FIG. 9a) disposed between the thermal interface material (radiation block 6) and the device (chip 3); and a second metallic layer (metallic substrate 71 as shown in FIG. 22) disposed between the thermal interface material (radiation block 6) and the lid (case 72). Regarding claim 4, Soyano shows a structure, comprising, wherein the lid comprises an inlet (terminal 83/85 as shown in FIG. 25), an outlet and flow channels (terminal 83/85), the flow channels are in communication with the inlet and the outlet (see FIG. 25). Regarding claim 5, Soyano shows a structure, comprising, wherein the device further comprises a semiconductor die (chip 3) laterally encapsulated by an inner insulating encapsulation (sealing 9) and an interposer (element 2bb), and the semiconductor die (chip 3) is disposed on and electrically connected to the interposer (element 2bb). Allowable Subject Matter Claims 10-20 are allowed. Regarding claim 10, Soyano fails to teach a reinforcement structure embedded in the insulating encapsulation wherein the heat sink is fastened to the reinforcement structure through screws. Regarding claim 18, Soyano also fails to teach a thermal interface material disposed between the semiconductor die and the lid, wherein a minimum distance between the lid and the first substrate substantially equals a sum of a maximum thickness of the outer insulating encapsulation and a thickness of the thermal interface material. Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 09, 2024
Application Filed
Aug 28, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745497
LIGHT EMITTING CHIP AND MANUFACTURING METHOD FOR THE SAME, AND LIGHT EMITTING DEVICE
3y 6m to grant Granted Sep 22, 2026
Patent 12740442
VIA STRUCTURE FOR EMBEDDED COMPONENT AND METHOD FOR MAKING SAME
4y 3m to grant Granted Sep 15, 2026
Patent 12733519
MULTICHIP MODULE THERMAL MANAGEMENT THROUGH BACKSIDE METAL
3y 5m to grant Granted Sep 08, 2026
Patent 12733550
POWER ELECTRONICS ARRANGEMENT WITH PARALLEL CONNECTED SEMICONDUCTOR SWITCHES, POWER ELECTRONICS DEVICE, MOTOR VEHICLE, AND METHOD FOR PRODUCING A POWER ELECTRONICS ARRANGEMENT
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Patent 12733361
SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
2y 10m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.8%)
2y 4m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 858 resolved cases by this examiner. Grant probability derived from career allowance rate.

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