Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
The first subparagraph of Claim 1 states “the dummy gate structure having a first sidewall and a second sidewall opposite the first sidewall”. In the drawings, the first sidewall is 118 and the second sidewall is 118 (¶ 0024 “Further in Figure 3…118…formed on sidewalls of the dummy gates 114 and the respective masks 116.”, ¶ 0026 “In Figure 4, gate spacers 120 are formed on…118”).
The fourth subparagraph of Claim 1 states “replacing the dummy gate structure with a replacement gate structure”. However, the drawings do not show that the first and second sidewalls (118) of the dummy gate structure are replaced (¶ 0035 “In Figure 9, the dummy gates 114 and the masks 116 (see Figure 8) are removed in an etching step(s), so that openings 128 are formed.”). More specifically, Figs. 3-13, 15-17, 21, and 24-27 show and label element 118.
Therefore, “replacing the dummy gate structure with a replacement gate structure” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 recites “The method of claim 4, wherein the liner layer and the buttress layer is a metal oxide.” However, Claim 4 recites “wherein one of the liner layer and the buttress layer is silicon nitride”. Therefore, both of the liner and buttress layers can not be a metal oxide (Claim 6) if one of them is required to be silicon nitride (Claim 4).
In addition, Claim 1 recites “the buttress layer comprising a metal nitride material or a silicon nitride material”. Therefore Claim 6 can not state “the buttress layer is a metal oxide.”
For purposes of compact prosecution, Claim 6 will be interpreted to instead recite “The method of claim --1-- [[4]], wherein the liner layer
Claim 20 recites “The method of claim 15, wherein after etching”. However, Claim 15 doesn’t have a method step that comprises “etching”.
For purposes of compact prosecution, Claim 20 will be interpreted to instead recite “The method of claim 19 [[15]], wherein after etching”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No.12,087,838. Although the claims at issue are not identical, they are not patentably distinct from each other.
Pending Claim 1 recites:
A method comprising:
forming a dummy gate structure over an active region of a substrate, the dummy gate structure having a first sidewall and a second sidewall opposite the first sidewall;
forming a first spacer structure on the first sidewall of the dummy gate structure;
forming a second spacer structure on the second sidewall of the dummy gate structure;
replacing the dummy gate structure with a replacement gate structure;
recessing the replacement gate structure to form a recess interposed between the first spacer structure and the second spacer structure; and
forming a hard mask in the recess, wherein forming the hard mask comprises:
forming a liner layer along sidewalls and a bottom of the recess; and
forming a buttress layer over the liner layer in the recess, the buttress layer comprising a metal nitride material or a silicon nitride material.
Claim 15 of patent ‘118 claims all the limitations as described in pending Claim 1 supra, and includes further limitations that are not specifically claimed in the present application. Therefore, the claims of patent ‘118 read on the presently filed application, but the claim limitations are not exactly the same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6, 8-12, 14-15, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liang et al. (“Liang”), US 2020/0105577.
Regarding Claim 1, Liang discloses a method (¶ 0005 “FIGS. 1 to 25C illustrate a method for manufacturing a semiconductor device”) comprising:
forming a dummy gate structure (200; Fig. 8; ¶ 0021 “form dummy gate structures 200”) over (¶ 0021 “200 wrapping the semiconductor fins 150”) an active region (150; Fig. 8; ¶ 0021 “semiconductor fins 150”) of a substrate (110; Fig. 8; ¶ 0018 “substrate 110”), the dummy gate structure (200) having a first sidewall (the left vertical side of 200; Fig. 8; ¶ 0021 “200 have substantially parallel longitudinal axes that are substantially perpendicular to longitudinal axes of the semiconductor fins 150, as illustrated in FIG. 8”; ¶ 0022 “sidewalls of the dummy gate structures 200”) and a second sidewall (the right vertical side of 200; Fig. 8; ¶ 0021 “200 have substantially parallel longitudinal axes that are substantially perpendicular to longitudinal axes of the semiconductor fins 150, as illustrated in FIG. 8”; ¶ 0022 “sidewalls of the dummy gate structures 200”) opposite the first sidewall (Fig. 8; ¶ 0022 “opposite sidewalls of the dummy gate structures 200”);
forming a first spacer structure (210; Fig. 9; ¶ 0022 “spacers 210”) on the first sidewall (Fig. 9) of the dummy gate structure (Fig. 9; ¶ 0022 “spacers 210 are formed on opposite sidewalls of the dummy gate structures 200”);
forming a second spacer structure (210; Fig. 9; ¶ 0022 “spacers 210”) on the second sidewall (Fig. 9) of the dummy gate structure (Fig. 9; ¶ 0022 “spacers 210 are formed on opposite sidewalls of the dummy gate structures 200”);
replacing (¶ 0033 “using a gate-last process, the dummy gate structures 200 is replaced by the final gate stack 290 at a subsequent step”) the dummy gate structure (200) with a replacement gate structure (290; Figs. 16A-16B; ¶ 0033 “final gate stack 290”);
recessing (Figs. 17A-17B; ¶ 0036 “An etching back process is performed to remove portions of the gate stacks 290”) the replacement gate structure (290) to form a recess (O3; Figs. 17A-17B; ¶ 0036 “openings O3 are formed”) interposed between (Fig. 17B; ¶ 0036 “the top surface of the gate stacks 290 is at a level lower than the top surfaces of the gate spacers 210”) the first spacer structure (210) and the second spacer structure (210); and
forming a hard mask (312, 316; Figs. 18B, 19B; ¶ 0039 “layer 312…and…layer 316 are formed sequentially) in the recess (Figs. 18B, 19B; ¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3”), wherein forming the hard mask comprises:
forming a liner layer (312; Figs. 18B, 19B; ¶ 0039 “layer 312”) along sidewalls and a bottom of the recess (Figs. 18B, 19B; ¶ 0039 “layer 312…formed sequentially in the openings O3 by suitable deposition process”); and
forming a buttress layer (316; Figs. 18B, 19B; ¶ 0039 “layer 316”) over the liner layer in the recess (Figs. 18B, 19B; ¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3”), the buttress layer comprising a metal nitride material or a silicon nitride material (¶ 0039 “layer 316 may be…nitride”).
Regarding Claim 2, Liang discloses wherein forming the liner layer (312) comprises performing an atomic layer deposition process (¶ 0039 “layer 312…are formed sequentially in the openings O3 by suitable deposition process, such as…ALD”).
Regarding Claim 4, Liang discloses wherein one of the liner layer and the buttress layer is silicon nitride (¶ 0039 “layer 312 and…layer 316 may be…nitride”).
Regarding Claim 5, Liang discloses wherein an other one of the liner layer and the buttress layer is a metal nitride (¶ 0039 “layer 312 and…layer 316 may be…nitride, oxynitride”).
Regarding Claim 6, Liang discloses wherein the liner layer and the buttress layer is a metal oxide (¶ 0039 “layer 312 and…layer 316 may be oxide” and “layer 312 and…layer 316 can be made of the same material”).
Regarding Claim 8, Liang discloses a method (¶ 0005 “FIGS. 1 to 25C illustrate a method for manufacturing a semiconductor device”) comprising:
forming a gate structure (290; Figs. 16A-16B; ¶ 0033 “final gate stack 290” and “plurality of layers included in the gate stacks 290 may be sequentially deposited”) over an active region (150; Fig. 19B; ¶ 0021 “wrapping the semiconductor fins 150”) of a substrate (110, Fig. 19B; ¶ 0042 “substrate 110”), spacer structures (212; Fig. 9; ¶ 0022 “210 is a multilayered structure that includes a first layer 212”) along sidewalls of the gate structure (Fig. 19B), and a dielectric layer (214; Fig. 9; ¶ 0022 “210 is a multilayered structure that includes…a second layer 214”) along sidewalls of the spacer structures (Fig. 9; ¶ 0022 “210 is a multilayered structure that includes a first layer 212 and a second layer 214”), an upper surface of the gate structure (290) being lower than (Figs. 17A-17B; ¶ 0036 “the top surface of the gate stacks 290 is at a level lower than the top surfaces of the gate spacers 210”) an upper surface of the dielectric layer (214 of 210) to form a recess (O3; Figs. 17A-17B; ¶ 0036 “openings O3 are formed”); and
forming a mask (312, 316, 340; Figs. 18B, 19B, 22B; ¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3”; ¶ 0044 “340 is formed over the substrate 110 and covers the…structure 310” ) over (Fig. 22B) the gate structure (290), wherein forming the mask comprises:
forming a liner layer (312; Figs. 18B, 19B, 22B; ¶ 0039 “layer 312”) along sidewalls and a bottom of the recess (Figs 18B, 19B, 22B; ¶ 0039 “layer 312…are formed sequentially in the openings O3 by suitable deposition process”);
forming a buttress layer (316; Figs. 18B, 19B, 22B; ¶ 0039 “layer 316”) over the liner layer in the recess (Figs. 18B, 19B; ¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3 by suitable deposition process”), the buttress layer being a different material than the liner layer (¶ 0039 “layer 316 may include…ZrO2” in this instance liner layer is silicon nitride and buttress layer is zirconium oxide); and
forming a capping layer (340; Fig. 22B; ¶ 0044 “340 is formed over the substrate 110 and covers the…structure 310”) over the buttress layer (Fig. 22B; ¶ 0044 “340…covers the…structure 310”), the capping layer being a different material than the buttress layer (¶ 0044 “340 is…silicon nitride, silicon nitride doped with carbon, silicon oxide, silicon oxynitride, silicon oxynitride doped with carbon, amorphous carbon material, silicon carbide, other nitride materials, other carbide materials, aluminum oxide, other oxide materials, other metal oxides, boron nitride, boron carbide, and other low-k dielectric materials or low-k dielectric materials doped with one or more of carbon, nitrogen, and hydrogen and/or other suitable materials” in this instance capping layer is silicon nitride).
Regarding Claim 9, Liang discloses wherein the buttress layer comprises a metal nitride material or a metal oxide material (¶ 0039 ““layer 316 may include…ZrO2””).
Regarding Claim 10, Liang discloses wherein the liner layer and the capping layer are formed of a same material (¶ 0039, 0044 in this instance silicon nitride).
Regarding Claim 11, Liang discloses wherein the liner layer and the buttress layer are formed using an atomic layer deposition process (¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3 by suitable deposition process, such as…ALD”) or a plasma-enhanced atomic layer deposition process.
Regarding Claim 12, Liang discloses wherein the liner layer comprises a first nitride material (¶ 0039 in this instance silicon nitride), the buttress layer comprises a second nitride material or a first oxide material (¶ 0039 in this instance zirconium oxide), and the capping layer comprises a third nitride material (¶ 0044 in this instance boron nitride).
Regarding Claim 14, Liang discloses wherein the buttress layer comprises TaN, TiN, AlN, ZrN, TiO, HfO, AlO, or ZrO (¶ 0039 “layer 316 may include HfO2, ZrO2, and Al2O3”).
Regarding Claim 15, Liang discloses a method (¶ 0005 “FIGS. 1 to 25C illustrate a method for manufacturing a semiconductor device”) comprising:
forming a gate structure (290; Figs. 16A-16B; ¶ 0033 “final gate stack 290” and “plurality of layers included in the gate stacks 290 may be sequentially deposited”) over an active region (150; Fig. 19B; ¶ 0021 “wrapping the semiconductor fins 150”) of a substrate (110; Fig. 19B; ¶ 0042 “substrate 110”), a first spacer structure (212; Fig. 9; ¶ 0022 “210 is a multilayered structure that includes a first layer 212”) and a second spacer structure (212; Fig. 9; ¶ 0022 “210 is a multilayered structure that includes a first layer 212”) along opposing sidewalls of the gate structure (Fig. 19B; ¶ 0022 “formed on opposite sidewalls of the…gate”), and a dielectric layer (214; Fig. 9; ¶ 0022 “210 is a multilayered structure that includes…a second layer 214”) along sidewalls of the first and second spacer structures (Fig. 9; ¶ 0022 “210 is a multilayered structure that includes a first layer 212 and a second layer 214”), an upper surface of the gate structure (290) being lower than (Figs. 17A-17B; ¶ 0036 “top surface of the gate stacks 290 is at a level lower than the top surfaces of the gate spacers 210”) an upper surface of the dielectric layer (214 of 210) to form a recess (O3; Figs. 17A-17B; ¶ 0036 “openings O3 are formed”); and
forming a mask (312, 316; Figs. 18B, 19B; ¶ 0039 “layer 312…and…316 are formed sequentially in the openings O3 by suitable deposition process”) over (Figs. 18B, 19B) the gate structure (290), wherein forming the mask comprises:
forming a first silicon nitride layer (312; Figs. 18B, 19B; ¶ 0039 “layer 312…may be…nitride”) along sidewalls and a bottom of the recess (Figs. 18B, 19B; ¶ 0039 “layer 312…formed sequentially in the openings O3 by suitable deposition process”); and
forming a metal nitride layer (316; Figs. 18B, 19B; ¶ 0039 “layer 316 may be…nitride”) over the first silicon nitride layer (Figs. 18B, 19B; ¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3 by suitable deposition process”).
Regarding Claim 18, Liang discloses wherein the first silicon nitride layer and the metal nitride layer are formed using an atomic layer deposition process (¶ 0039 “layer 312…and…layer 316 are formed sequentially in the openings O3 by suitable deposition process, such as…ALD”) or a plasma-enhanced atomic layer deposition process.
Regarding Claim 19, Liang discloses further comprising:
etching (¶ 0046 “an etching process is performed to form an opening O5”) the dielectric layer (214 of 210; ¶ 0046 “In practice, the openings O5…may be arranged at a desired position” in this instance a portion of layer 214 of 210 is etched to make the opening O5 as large as possible to improve the electrical connection between the gate structure 290 and the subsequently formed conductive via 380 thereby improving the performance and reliability of the device), wherein etching the dielectric layer removes a portion of the first silicon nitride layer and the metal nitride layer (¶ 0046 “after the etching process, the…layer 312…and the…layer 316…are exposed from the opening O5”).
Regarding Claim 20, Liang discloses wherein after etching (Fig. 23B), an upper surface of the first silicon nitride layer (312) is higher than (Fig. 23B) an upper surface of the first spacer structure (212 of 210).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3, 7, 13, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (“Liang”), US 2020/0105577.
Regarding Claim 3, Liang does not specifically disclose wherein forming the liner layer comprises a plasma-enhanced atomic layer deposition process.
¶ 0039 teaches that any “”suitable deposition process” including “ALD” can be used to form the liner layer 312. Therefore, it would be obvious to use plasma-enhanced ALD because PEALD is known to provide faster deposition rates, better conformality, and better uniformity with lower processing temperatures.
Regarding Claim 7, Liang discloses wherein the liner layer and the buttress layer completely fill the recess (Fig. 17B; ¶ 0039 “layer 312…and…316 are formed sequentially in the openings O3 by suitable deposition process”; ¶ 0040 “planarization process, such as CMP, is performed to remove excessive materials of the…layer 312…and the…layer 316”).
Liang does not specifically disclose wherein an upper surface of the liner layer and an upper surface of the buttress layer are level with an upper surface of the first spacer structure.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would be an obvious variant to form all of the 310 structure in the recess between the top portions of the first spacer structure 210 and the second spacer structure 210 in order to reduce the manufacturing cost of the method and to form a more compact semiconductor device.
Regarding Claim 13, Liang does not specifically disclose wherein the liner layer has a thickness in a range of 2 nm to 10 nm, wherein the buttress layer has a thickness in a range of 2 nm to 10 nm.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Liang discloses “first insulating layer 312, a sacrificial layer 314, and a second insulating layer 316 are formed sequentially in the openings O3 by suitable deposition process, such as PVD, CVD, and ALD” (¶ 0039). Liang also discloses “the thickness of the sacrificial layer 314 is in a range from about 1 nm to about 3 nm. For example, the sacrificial layer 314 is about 2 nm” (¶ 0039). It would be obvious to form all three layers 312, 314, and 316 having the same thickness, in a range of 2 nm to 3 nm, because they’re formed in-situ and forming the three layers having the same thickness would be a simplified manufacturing process, thereby reducing manufacturing costs.
Regarding Claim 16, Liang discloses further comprising: forming a second silicon nitride layer (340; Fig. 22B; ¶ 0044 “340 is…silicon nitride”) over the metal nitride layer.
Liang does not specifically disclose wherein an upper surface of the second silicon nitride layer is level with an upper surface of the dielectric layer.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would be an obvious variant to form layer 340 and all of the 310 structure in the recess between the top portions of the dielectric layer of 210 in order to reduce the manufacturing cost of the method and to form a more compact semiconductor device.
Regarding Claim 17, Liang does not specifically disclose wherein the second silicon nitride layer is thicker than the first silicon nitride layer and the metal nitride layer.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would be obvious to have the second silicon nitride layer thicker than the first silicon nitride layer and the metal nitride layer because silicon nitride is an excellent electrical insulator that is suitable for high-voltage applications, thereby improving the versatility, performance, and reliability of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yang et al US 2020/0105938 discloses a method that includes forming a dummy gate structure over an active layer of a substrate, replacing the dummy gate structure with a replacement gate structure, forming a spacer structure, and forming a hard mask over the replacement gate structure. Ho et al. US 9,548,366 discloses a method that includes forming a dummy gate structure over an active layer of a substrate, replacing the dummy gate structure with a replacement gate structure, forming a spacer structure, recessing the replacement gate structure, and forming hard mask layers over the replacement gate structure. Chang et al. US 2020/0135462 discloses a method that includes forming a gate structure over an active layer of a substrate, and forming hard mask layers over the gate structure.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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