DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 12-13, 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 11,424,271 to Nishida et al. (hereafter Nishida).
Regarding independent claim 1, Nishida teaches a method for waking up ferroelectric memory (see FIGS. 5A-5B, 6:21-7:47), comprising steps of:
forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cells includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode (see FIG. 1 and 3:4 1-4:3), and the ferroelectric structure inherently includes a cluster of vacancies or traps that obstruct reversals of electric dipoles around the cluster of vacancies or traps (see 7:6-47); and
applying a voltage signal to the ferroelectric memory cell to induce an electric field in the ferroelectric structure, thereby spreading out the cluster of vacancies or traps (see FIGS. 5A-5B and 6:21-7:47).
Regarding dependent claim 2, Nishida teaches wherein the electric field in the ferroelectric structure, which is induced by the applying of the voltage signal, is in a range between 2×106 volts/cm and 6×106 volts/cm (FIG. 5B: absolute value of maximum electric field is between 2-4 MV/cm as shown).
Regarding dependent claim 3, Nishida teaches wherein the ferroelectric structure has a thickness in a range from 5 nm to 20 nm (10 nm, see 6:43-47), and the applying of the voltage signal results in a voltage across the ferroelectric structure ranging from 1 volt to 12 volts (FIG. 5A: applied voltage is between 3-4 volts).
Regarding independent claim 12, Nishida teaches a method for waking up ferroelectric memory, comprising steps of:
forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cells includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode (see FIG. 1 and 3:4 1-4:3); and
applying a voltage signal to the ferroelectric memory cell to rise a percentage of molecules of a ferroelectric phase in the ferroelectric structure (see FIGS. 5A-5B and 6:21-7:47) to a range from 50% to 100% (this is obvious because wake-up process is to make the ferroelectric memory operable for storing information, see 7:6-47).
Regarding dependent claim 13, Nishida teaches wherein the voltage signal induces an electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm (FIG. 5B: absolute value of maximum electric field is between 2-4 MV/cm as shown).
Regarding independent claim 17, Nishida teaches a method for waking up ferroelectric memory, comprising steps of:
forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cells includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode (see FIG. 1 and 3:4 1-4:3); and
applying a voltage signal to the ferroelectric memory cell to increase each of a positive remnant polarization value and a negative remnant polarization value of the ferroelectric structure in magnitude (see FIGS. 5A-5B and 6:21-7:47).
Regarding dependent claim 18, Nishida teaches wherein the voltage signal induces an electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm (FIG. 5B: absolute value of maximum electric field is between 2-4 MV/cm as shown).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-9, 14-15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of US 10,153,054 to Mariani et al. (hereafter Mariani).
Regarding dependent claim 4, Nishida further teaches wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive pulse group and a negative pulse group (i.e. PUND, see 6:43-47). However, Nishida doesn’t teach the remaining limitations of claim 4.
Mariani teaches a method for recovering fatigued ferroelectric memory by applying fatigue recovery pulse(s) to the ferroelectric memory cell. The fatigue recovery pulse(s) may comprise one of the pulses 410, 410-a and 410-b of FIG. 4. Fatigue recovery pulse 410-b in FIG. 4 of Mariani is similar to the wake-up pulse in FIG. 5A of Nishida. Mariani particularly describes fatigue recovery pulse 410 comprise a positive pulse group includes a plurality of
Since Nishida and Mariani are both from the same field of endeavor, the purpose disclosed by Mariani would have been recognized in the pertinent art of Nishida.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that wake-up and fatigue recovery are seen functional equivalent because they are both to inverse an imprint phenomenon. It also would have been obvious to realize that it’s functional equivalent to break up the fatigue recovery pulse 410 in FIG. 4 of Mariani into consecutive positive voltage pulses, following with consecutive negative voltage pulses as long as they provide required electric charges during the time period.
Regarding dependent claim 5, Nishida teaches wherein positive voltage pulse induces the electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm in magnitude, and negative voltage pulse induces the electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm in magnitude (see FIG. 5B).
Regarding dependent claims 6-9, Mariani does not explicitly teaches wherein the consecutive positive/negative voltage pulses in the positive pulse group are different from each other in pulse width/magnitude. However, it would have been obvious to one with ordinary skill in the art to combine fatigue recovery pulses 410, 410-a and 410-b in FIG. 4 for any desire pulse sequence, pulse width, pulse magnitude or combination thereof as long as they provide required electric charges for the reverse imprint process during a given period of time.
Regarding dependent claims 14-15 and 19, see rejections applied to claims 6-8 above.
Allowable Subject Matter
Claims 11, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 11: wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts; and wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion.
With respect to dependent claim 16: wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts; and wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion.
With respect to dependent claim 20: wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts; and wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion.
Conclusion
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December 23, 2025
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824