DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1, 3, 5-7, 11, 14 and 18 have been amended.
Objections to the Claims
Amendments made to claim(s) have overcome the previous objections. Claim(s) 1 and 11 are no longer objected.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 07/15/2026 with respect to Claim(s) 1-18 have been fully considered but they are not persuasive.
Applicant(s) have amended independent claim(s) 1, 11 and 18 to patentably distinguish over prior art of XIAO alone or in combination with others, however the Examiner believes that XIAO alone or in combination with others teaches the amended limitations.
As to applicant(s) argument of “The references themselves do not disclose or fairly suggest that the DRAM cells of the DRAM of Xiao are "IC dies", and the Office Action has provided no evidence that those skilled in the art would reach the conclusion that the DRAM cells of the DRAM of Xiao are "IC dies".”, the Examiner respectfully disagrees. XIAO teaches DRAM circuit on IC wafer and it is common knowledge in the art that IC dies are the individual pieces of cut silicon (the "chip") that can house an organized matrix of millions or billions of these DRAM cells alongside supporting peripheral on a wafer substrate.
(see abs., para. 3 of XIAO - integrated circuit chip manufacturing … detect voltage contrast (VC) defects of electrical circuitry such as open circuit, short circuit or leakage underneath the wafer surface because of surface charge induced gray level (GL) variation;
BLAIR et al. (US 20240224542) para. 2 - Conventional chip packaging schemes often utilize a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic, processor or other IC devices;
JUNG et al. (US 20200092509) para. 10 - a multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM;
PU et al. (US20230076943) step S105 in fig. 6 and para. 23 - test structures were placed in the scribe lines because they were too large to be placed inside the individual dies without interfering with their eventual operation).
Therefore, Examiner believes prior arts teaches said limitation.
Based on the arguments presented above, the Examiner strongly believes XIAO alone or in combination with others meets the current limitations for Claim(s) 1-18.
For further details see the rejections/objections for Claim(s) 1-18 herein.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-14 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2008/0265251 to XIAO et al. (hereinafter XIAO) or, in the alternative, under 35 U.S.C. 103 as obvious over XIAO in view of BLAIR et al. (US 20240224542).
Regarding claim 11, XIAO teaches a device (para. 0005 :- a structure and method for determining a defect in integrated circuit manufacturing process), comprising:
a semiconductor wafer (wafer at para. 0003); and
an array of integrated circuit (IC) dies (para. 15 – DRAM cells; word lines figs. 3A-3B, 5) disposed on a surface of the semiconductor wafer and voltage contrast electron beam inspection (VC-EBI) test patterns (paras. 2,16,32 – test patterns; figs. 5-12) disposed on the surface of the semiconductor wafer between the IC dies (IC process and wafer at para. 0003; It is common knowledge in the art that IC die is the individual piece of cut silicon (the "chip") that houses an organized matrix of millions or billions of these DRAM cells alongside supporting peripheral. DRAM arrays or DRAM cells and controllers can be manufactured in multi-IC dies configuration. Thereby, Xiao’s first dram array is interpreted as a first IC die and second array or controller is a second IC die. Thus detecting defect between IC dies; See also BLAIR et al. (US 20240224542) para. 2 - Conventional chip packaging schemes often utilize a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic, processor or other IC devices), wherein the the VC-EBI test patterns include:
an N+/P structure (paras. :- 0034-0036; NMOS device 250 figs. 2B,3A) comprising at least one active structure formed with P-type doping (p-type doped channel 258) in contact with at least one first source/drain structure of N-type doping (N-doped Source 260 @left) arranged next to an N+/N structure (N+/N well 301 in Fig. 3B) comprising at least one active structure formed with N-type doping (N+/N well 301 in Fig. 3B) in contact with the at least one second source/drain structure of N-type doping (N-doped Drain 260 @right); and an N+/N well structure (N+/N well 301 in Fig. 3B) comprising at least one active structure formed with N-type doping (N+/N well 301 in Fig. 3B) in contact at least one second source/drain structure of N-type doping (N-doped Drain 260 @right), wherein the at least one second source/drain structure of N-type doping is arranged next to the at least one first source/drain structure of N-type doping (abs., para. 0008-0012; NMOS device 250 arrays; Figs. 2B and 3A); and/or
a P+/N structure comprising at least one active structure formed with N-type doping (Fig. 2A channel 208) in contact with at least one first source/drain structure of P-type doping (Fig. 2A, S/D 210) and a P+/P structure comprising at least one active structure formed with P-type doping in contact at least one second source/drain structure of P-type doping (para. 0044 :- while the defective active areas may be active areas of semiconductor devices having heavily p-type doped source and drain, and p-type doped well P+/P- well), wherein the at least one second source/drain structure of P-type doping is arranged next to the at least one first source/drain structure of P-type doping (abs., para. 0008-0012 :- PMOS device 200 arrays; Figs. 2A).
lllustrated below are Figs. 2A-2B and 3A-3B of XIAO, marked and annotated for the convenience of the applicant.
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XIAO teaches everything except explicitly reciting dies.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have pattern disposed between IC dies as it is a matter of common knowledge to have IC dies in order to test defect in semiconductor manufacturing (as evidenced by BLAIR et al. (US 20240224542) – see para. 27 - utilizing a 3D stack having a plurality of DRAM arrays 426 on a semiconductor die, i.e., DRAM-capacitor fabric 120, multiple identical dice can be stacked together, but then an individual die can be configured/allocated to function as either a traditional DRAM … individual stacks can be tested to determine which (if any) layers or sub-regions of layers are defective from a DRAM functionality; 426 in fig. 4).
Regarding claim 12, XIAO teaches wherein the VC-EBI test patterns include said N+/P structure arranged next to said N+/N structure (FIG. 3B).
Regarding claim 13, XIAO teaches wherein the VC-EBI test patterns include said P+/N structure arranged next to said P+/P structure (para. 0044 - while the defective active areas may be active areas of semiconductor devices having heavily p-type doped source and drain, and p-type doped well P+/P-well).
Regarding claim 14, XIAO teaches wherein the VC-EBI test patterns further include a
P+/N structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to an N+/P structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping (Figs. 2A and 2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C.102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-7, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US XIAO in view of US 20070197020 to Ramappa et al. (hereinafter Ramappa).
Regarding claim 1, XIAO teaches a semiconductor manufacturing method (para. 0002 - a method for determining a defect in integrated circuit manufacturing process), comprising:
providing a semiconductor wafer including an array of integrated circuit (IC) dies (para. 15 – DRAM cells; word lines figs. 3A-3B, 5) and voltage contrast electron beam inspection (VC-EBI) test patterns (paras. 2,16,32 – test patterns; figs. 5-12) disposed between the IC dies (IC process and wafer at para. 0003; It is common knowledge in the art that IC die is the individual piece of cut silicon (the "chip") that houses an organized matrix of millions or billions of these DRAM cells alongside supporting peripheral. DRAM arrays or DRAM cells and controllers can be manufactured in multi-IC dies configuration. Thereby, Xiao’s first dram array is interpreted as a first IC die and second array or controller is a second IC die. Thus detecting defect between IC dies; See also BLAIR et al. (US 20240224542) para. 2 - Conventional chip packaging schemes often utilize a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic, processor or other IC devices), wherein the VC-EBI test patterns include an N+/P structure (paras. - 0034-0036; NMOS device 250 figs. 2B,3A) comprising at least one active structure formed with P-type doping (p-type doped channel 258) in contact with at least one first source/drain structure of N-type doping (N-doped Source 260 @left) arranged next to an N+/N structure (N+/N well 301 in Fig. 3B) comprising at least one active structure formed with N-type doping (N+/N well 301 in Fig. 3B) in contact with the at least one second source/drain structure of N-type doping (N-doped Drain 260 @right); and
receiving a plurality of images by applying an electron beam to the VC-EBI test patterns (Fig. 4; paras. 0003 and 0041 - images are obtained using electron beam inspection (EBI) and the images are used for determining target defects; paras. 0005-0007 - detect electrical short between contact plugs …void-induced short or a non-open contact of the normal active areas).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have pattern disposed between IC dies as it is a matter of common knowledge to have IC dies in order to test defect in semiconductor manufacturing (as evidenced by BLAIR et al. (US 20240224542) – see para. 27 - utilizing a 3D stack having a plurality of DRAM arrays 426 on a semiconductor die, i.e., DRAM-capacitor fabric 120, multiple identical dice can be stacked together, but then an individual die can be configured/allocated to function as either a traditional DRAM … individual stacks can be tested to determine which (if any) layers or sub-regions of layers are defective from a DRAM functionality).
XIAO fails to teach transferring the semiconductor wafer to a next process step if the plurality of images do not indicate a short between the first source/drain structure of N-type doping and the second source/drain structure of N-type doping.
However, Ramappa teaches in figure(s) 1-5 transferring the semiconductor substrate to a next process step (process steps 170, 190 in figs. 1) if plurality of images do not indicate a short (process step 130; para. 18 - semiconductor substrate, such as a silicon wafer the semiconductor devices can comprise nMOS, pMOS transistors or CMOS devices, having metal interconnects, such as contacts, formed on source and drain structures and gate structures; para. 23 - Two interconnect features affected by a shorting type of reliability defect tend to look brighter (voltage contrast bright). When a beam rasters a given area) between the first source/drain structure of N-type doping and the second source/drain structure of N-type doping (para. 46 - semiconductor device 310 comprise an nMOS transistor 330 and a pMOS transistor 335 that form a semiconductor device 310 that is a CMOS device; para. 33 - characterize the defect's severity … that causes a short circuit or other malfunction in the semiconductor device; fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of XIAO by having transferring the semiconductor substrate to a next process step if plurality of images do not indicate a short between the first source/drain structure of N-type doping and the second source/drain structure of N-type doping as taught by Ramappa in order to provide inline method for testing semiconductor defects during manufacturing process as evidenced by "A method of manufacturing an integrated circuit comprising: wherein said voltage contrast image is obtained using a collection field that is at least about 1 percent different than an incident field; and using said voltage contrast image to determine the presence of an interconnect defect in said semiconductor device … wherein further back-end-of-line processing of said semiconductor device is halted if said interconnect defect is detected… wherein one or more steps in said back-end-of-line process are modified if said interconnect defect is detected." (clm. 17-20 of Ramappa).
Regarding claim 18, XIAO teaches a semiconductor manufacturing method (para. 0002 - a method for determining a defect in integrated circuit manufacturing process), comprising:
providing a semiconductor wafer including an array of integrated circuit (IC) dies (para. 15 – DRAM cells; word lines figs. 3A-3B, 5) and voltage contrast electron beam inspection (VC-EBI) test patterns (paras. 2,16,32 – test patterns; figs. 5-12) disposed between the IC dies (IC process and wafer at para. 0003; It is common knowledge in the art that IC die is the individual piece of cut silicon (the "chip") that houses an organized matrix of millions or billions of these DRAM cells alongside supporting peripheral. DRAM arrays or DRAM cells and controllers can be manufactured in multi-IC dies configuration. Thereby, Xiao’s first dram array is interpreted as a first IC die and second array or controller is a second IC die. Thus detecting defect between IC dies; See also BLAIR et al. (US 20240224542) para. 2 - Conventional chip packaging schemes often utilize a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic, processor or other IC devices), wherein the VC-EBI test patterns include an P+/N structure (paras. - 0034-0036; NMOS device 250 figs. 2B,3A) comprising at least one active structure formed with N-type doping (N-doped Source 260 @left) in contact with at least one first source/drain structure of P-type (p-type doped channel 258) doping arranged next to an P+/P structure comprising at least one active structure formed with P-type doping in contact with the at least one second source/drain structure of P-type doping (para. 0044 - while the defective active areas may be active areas of semiconductor devices having heavily p-type doped source and drain, and p-type doped well P+/P-well); and
receiving a plurality of images by applying an electron beam to the VC-EBI test patterns (Fig. 4; paras. 0003 and 0041 - images are obtained using electron beam inspection (EBI) and the images are used for determining target defects; paras. 0005-0007 - detect electrical short between contact plugs …void-induced short or a non-open contact of the normal active areas).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have pattern disposed between IC dies as it is a matter of common knowledge to have IC dies in order to test defect in semiconductor manufacturing (as evidenced by BLAIR et al. (US 20240224542) – see para. 27 - utilizing a 3D stack having a plurality of DRAM arrays 426 on a semiconductor die, i.e., DRAM-capacitor fabric 120, multiple identical dice can be stacked together, but then an individual die can be configured/allocated to function as either a traditional DRAM … individual stacks can be tested to determine which (if any) layers or sub-regions of layers are defective from a DRAM functionality).
XIAO fails to teach transferring the semiconductor wafer to a next process step if the plurality of images do not indicate a short between the first source/drain structure of P-type doping and the second source/drain structure of P-type doping.
However, Ramappa teaches in figure(s) 1-5 transferring the semiconductor substrate to a next process step (process steps 170, 190 in figs. 1) if plurality of images do not indicate a short (process step 130; para. 18 - semiconductor substrate, such as a silicon wafer the semiconductor devices can comprise nMOS, pMOS transistors or CMOS devices, having metal interconnects, such as contacts, formed on source and drain structures and gate structures; para. 23 - Two interconnect features affected by a shorting type of reliability defect tend to look brighter (voltage contrast bright). When a beam rasters a given area) between the first source/drain structure of P-type doping and the second source/drain structure of P-type doping (para. 46 - semiconductor device 310 comprise an nMOS transistor 330 and a pMOS transistor 335 that form a semiconductor device 310 that is a CMOS device; para. 33 - characterize the defect's severity … that causes a short circuit or other malfunction in the semiconductor device; fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of XIAO by having transferring the semiconductor substrate to a next process step if plurality of images do not indicate a short between the first source/drain structure of P-type doping and the second source/drain structure of P-type doping as taught by Ramappa in order to provide inline method for testing semiconductor defects during manufacturing process as evidenced by "A method of manufacturing an integrated circuit comprising: wherein said voltage contrast image is obtained using a collection field that is at least about 1 percent different than an incident field; and using said voltage contrast image to determine the presence of an interconnect defect in said semiconductor device … wherein further back-end-of-line processing of said semiconductor device is halted if said interconnect defect is detected… wherein one or more steps in said back-end-of-line process are modified if said interconnect defect is detected." (clm. 17-20 of Ramappa).
Regarding claim 3, XIAO teaches the semiconductor manufacturing method of claim 1 wherein the VC-EBI test patterns further include a P+/N structure comprising at least one active structure formed with N-type doping (Fig. 2A channel 208) in contact with at least one first source/drain structure of P-type doping (Fig. 2A, S/D 210) arranged next to a P+/P structure comprising at least one active structure formed with P-type doping in contact with at least one second source/drain structure of P-type doping (para. 0044 - while the defective active areas may be active areas of semiconductor devices having heavily p-type doped source and drain, and p-type doped well P+/P-well).
Regarding claim 4, XIAO teaches wherein the semiconductor wafer is a silicon (silicon is commonly known semiconductor wafer material; para. 33 - polysilicon landing pad plugs for semiconductor device 100) or silicon-on-insulator (SOI) wafer.
Regarding claim 5, XIAO teaches the semiconductor manufacturing method of claim 1 wherein the VC-EBI test patterns further include a P+/N structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a second N+/P structure comprising at least one active structure formed with P-type doping in contact at least one third source/drain structure of N-type doping (Figs. 2A and 2B).
Regarding claim 6, XIAO teaches the semiconductor manufacturing method of claim 1 wherein the VC-EBI test patterns further include an N+/P structure comprising at least one active structure formed with P-type doping in contact with at least one third source/drain structure of N-type doping arranged next to a second N+/P structure comprising at least one active structure formed with P-type doping in contact with the at least one fourth source/drain structure of N-type doping (two adjacent NMOS structures illustrated in Figs. 2B, 3B and 7B).
Regarding clam 7, XIAO teaches the semiconductor manufacturing method of claim 1 wherein the VC-EBI test patterns further include a P+/N structure comprising at least one active structure formed with N-type doping in contact with at least one first source/drain structure of P-type doping arranged next to a second P+/N structure comprising at least one active structure formed with N-type doping in contact at least one second source/drain structure of P-type doping (two adjacent PMOS structures illustrated in Figs. 2A, 3A and 7A).
Regarding claim 20, XIAO teaches the semiconductor manufacturing method of claim 18 wherein the VC-EBI test patterns further include a P+/N structure comprising at least one active structure formed with N-type doping (Fig. 2A channel 208) in contact with at least one third source/drain structure of P-type doping (Fig. 2A, S/D 210) arranged next to a N+/P structure comprising at least one active structure formed with P-type doping in contact with at least one source/drain structure of N-type doping (para. 0044 - while the defective active areas may be active areas of semiconductor devices having heavily p-type doped source and drain, and p-type doped well P+/P-well).
Claim(s) 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over XIAO in view of Ramappa, and further in view of US 7,635,843 to Luo et al. (hereinafter Luo).
Regarding claim 8, XIAO fails to teach wherein the providing comprises performing front end-of-line (FEOL) processing of an integrated circuit (IC) manufacturing process, and the next process step comprises a back end-of-line (BEOL) processing step.
In the same field of endeavor, Luo teaches that some defects in the FET are observable.
Electron-beam ("E-beam") inspection techniques are typically used to inspect process wafers during a fabrication sequence for gate oxide and other defects. Such inspection is commonly referred to as "in-line" because the inspection step is incorporated into the fabrication process flow. In other words, process wafers can be inspected between fabrication steps without removing the wafer from the fabrication area, such as between front-end-of-line ("FEOL") processes and back end-of-line ("BEOL") processes (col. 2, lines 14-23). That is, Luo teaches wherein the providing of the plurality of patterns on the semiconductor substrate comprises performing front end-of-line (FEOL) processing of an integrated circuit (IC) manufacturing process, and the next process step comprises a back end-of-line (BEOL) processing step.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified XIAO as taught by Luo. This would have been done to insect the wafers during the fabrication process flow, as taught by Luo at col. 2, lines 14-23.
Regarding claim 9, XIAO fails to teach wherein the VC-EBI test patterns are disposed on a surface of the semiconductor wafer and the active structures of the VC-EBI test patterns comprise mutually parallel linear fins each extending away from the surface of the semiconductor wafer, and the VC-EBI patterns further include gate lines crossing and oriented perpendicular to the linear fins.
However, Luo teaches that the patterns (Fig. 3A, pattern 300) are disposed on a surface of the semiconductor wafer (302) and the active structures (304) of the VC-EBI patterns comprise mutually parallel linear fins (310, 312, 314) each extending away from the surface of the semiconductor wafer, and the VC-EBI patterns further include gate lines crossing and oriented perpendicular to the linear fins (col. 5, lines, 2-6 and 16-19 - a gate dielectric layer is between the quasi-grounded polysilicon, the floating polysilicon and the active area 304, and is between the capacitor 316 and the active area 318).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified XIAO as taught by Luo. This would have been done to incorporate the test structure into the wafer, as taught by Luo at col. 4, lines 50-61.
Regarding claim 10, XIAO fails to teach wherein the patterns are disposed on a wafer that also has an array of integrated circuit (IC) dies disposed thereon, and the patterns are disposed between the IC dies.
On the same field of endeavor, Luo teaches that the wafer 200 includes test structures 204, 206 designed to indicate electrical stress defects after a stress scan in an E-beam system. Alternatively, test structures are incorporated into one or more ICs. The stress scan is limited to the test structures 204, 206. The test structure can be anywhere on the wafer. For example, the test structure 204 is within the alley 205 and test structure 206 is included in an IC. Alternatively, the wafer is a test wafer that is not intended to produce shippable ICs, but is designed to evaluate process conditions and layout dimensions. In that case, the stress scan can be applied to other areas in addition to the test structures 204, 206 (at col. 4, lines 50-61). That is, Luo teaches wherein the patterns are disposed on a wafer that also has an array of integrated circuit (IC) dies disposed thereon, and the patterns are disposed between the IC dies.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified XIAO as taught by Luo. This would have been done to incorporate the test structure into the wafer, as taught by Luo at col. 4, lines 50-61.
Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over XIAO in view of Luo.
Regarding claims 15 and 16, XIAO in view of Ramappa fails to teach wherein the active structures of the patterns comprise one or more mutually parallel fins disposed on the surface of the wafer. wherein the patterns further include gate lines crossing and oriented perpendicular to the fins.
However, Luo teaches that the patterns (Fig. 3A, pattern 300) are disposed on a surface of a substrate (302) and the active structures (304) of the patterns comprise mutually parallel linear fins (310, 312, 314) each extending away from the surface of the substrate, and the patterns further include gate lines crossing and oriented perpendicular to the linear fins (col. 5, lines, 2-6 and 16-19 - a gate dielectric layer is between the quasi-grounded polysilicon, the floating polysilicon and the active area 304, and is between the capacitor 316 and the active area 318).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified XIAO in view of Ramappa as taught by Luo. This would have been done to incorporate the test structure into the wafer, as taught by Luo at col. 4, lines 50-61.
Claim(s) 17 are rejected under 35 U.S.C. 103 as being unpatentable over XIAO in view of Pourkeramat.
Regarding claim 17, XIAO fails to teach further comprising: the VC-EBI test patterns are disposed in scribe lines between the IC dies.
However, Pourkeramat teaches the VC-EBI test patterns are disposed in scribe lines between the IC dies (abs. - a scanning pad scanned by an electron beam inspection tool and a test key. The structure can be located in the scribe line; horizontal scribe lines 104 and vertical scribe lines 106; figs. 1,3).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified XIAO as taught by Pourkeramat. This would have been done to incorporate wafer having multiple dies organized in rows and column separetd by scribe lines. After wafer sort good dies are extracted from the wafer by sawing along the vertical and horizontal scribe lines and then placed in the desired packages, as taught by Pourkeramat at col. 1, lines 30-40.
Claim(s) 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over XIAO in view of in view of Ramappa, and further in view of Pourkeramat.
Regarding claim(s) 2 and 19, XIAO in view of Ramappa fails to teach wherein the VC-EBI test patterns are disposed in scribe lines between the IC dies, and the next process step comprises dicing the semiconductor wafer along the scribe lines to separate the IC dies.
However, Pourkeramat teaches the VC-EBI test patterns are disposed in scribe lines between the IC dies (abs. - a scanning pad scanned by an electron beam inspection tool and a test key. The structure can be located in the scribe line; horizontal scribe lines 104 and vertical scribe lines 106 figs. 1,3), and the next process step comprises dicing the semiconductor wafer along the scribe lines to separate the IC dies (col. 1, lines 30-40 - good dies are extracted from the wafer by sawing along the vertical and horizontal scribe lines).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified XIAO in view of Ramappa as taught by Pourkeramat. This would have been done to incorporate wafer having multiple dies organized in rows and column separetd by scribe lines. After wafer sort good dies are extracted from the wafer by sawing along the vertical and horizontal scribe lines and then placed in the desired packages, as taught by Pourkeramat at col. 1, lines 30-40.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
BLAIR et al. (US 20240224542) discloses “A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration”.
JUNG et al. (US 20200092509) discloses “A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs.”.
PU et al. (US20230076943) discloses “in-die metrology target areas to identify defects in semiconductor fabrication and operation processes.”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on Monday - Friday; 8.00am - 5.00pm (EST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/Primary Examiner, Art Unit 2858
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