DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,087, 639. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of the present Application are anticipated by claims 1-20 of U.S. Patent No. 12,087, 639.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, and 10-19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Tung (US 2017/0278928).
Regarding claim 1, Tung discloses a semiconductor device comprising: a first fin (Fig.14, numeral 408’) over a substrate (300); a second fin (408’) over the substrate (400) and adjacent to the first fin (408’); a dummy fin (301)between the first fin (408’) and the second fin (408’) ([0031]); shallow trench isolation (STI) regions (302) between the first fin (408’) and the dummy fin (310), and between the second fin (408’) and the dummy fin (310); a first gate structure (412); (414) over the first fin (408’), wherein the first gate structure comprises a gate dielectric material (412) along a first sidewall of the first fin (408’) and along a first upper surface of the first fin (408’) , and comprises a first gate electrode (414) over the gate dielectric material (412); a second gate structure (512); (514) over the second fin (408’), wherein the second gate structure comprises the gate dielectric material (512) along a second sidewall of the second fin (408’) and along a second upper surface of the second fin (408’), and comprises a second gate electrode (514) over the gate dielectric material (512); and a dielectric structure (312) over the dummy fin (310), wherein the dielectric structure (312) is disposed between and contacts the first gate structure (414) and the second gate structure (514), wherein the dielectric structure (312) has an upper portion (upper part of (312)) and a lower portion (lower part of (312) of parts of (412) on (310); (304’’)) between the upper portion and the substrate (300), wherein a first width of the lower portion (parts of (412) on (310); (304’’) and lower part of (312)) is larger than a second width of the upper portion (upper part of (312)).
Regarding claim 2, Tung discloses wherein the dielectric structure (412) ;(312); (304’’) contacts the dummy fin (310).
Regarding claim 3, Tung discloses wherein an upper surface of the first fin (408’) extends further from the substrate (300) than a lower surface of the dielectric structure (304’’) facing the substrate (300).
Regarding claim 4, Tung discloses wherein an upper surface of the dielectric structure (312) distal from the substrate (300) is level with an upper surface of the first gate structure (414) distal from the substrate (300).
Regarding claim 5, Tung discloses wherein an upper surface of the second gate (514) structure is level with the upper surface of the first gate structure (414) (Fig.14).
Regarding claim 6, Tung discloses wherein a first longitudinal direction of the first gate structure (412); (414) and a second longitudinal direction of the second gate (512); (514) structure extend along a same line (Fig.14).
Regarding claim 7, Tung discloses wherein the first width is measured along the first longitudinal direction of the first gate structure (412); (414), and the second width is measured along the second longitudinal direction of the second gate structure (512); (514).
Regarding claim 8, Tung discloses wherein the lower portion of the dielectric structure (412); (312) and the upper portion of the dielectric structure (312) have a same width measured along a direction perpendicular to the first longitudinal direction.
Regarding claim 10, Tung discloses wherein the lower portion of the dielectric structure (304’’) has an oval shaped, a diamond shaped, or a rectangular shaped cross-section (Fig. 1, numeral 312).
Regarding claim 11, Tung discloses a semiconductor device comprising: a first fin (Fig.14, numeral 408’) , a second fin (408’) , and a dummy fin (310) that protrude above a substrate (300), wherein the dummy fin (310) is between the first fin (408’) and the second fin (408’); isolation regions (304’’) on opposing sides of the first fin (408’), the second fin (408’), and the dummy fin (310), wherein the isolation regions (304’’) contact and extend along first sidewalls of the first fin (408’), second sidewalls of the second fin (408’), and third sidewalls of the dummy fin (310); a first gate structure (412); (414) and a second gate structure (514) over the first fin and the second fin, respectively, wherein the first gate structure comprises a gate dielectric material (412) along the first sidewalls of the first fin (408’) and along a first upper surface of the first fin (408’), and comprises a first gate electrode (414) over the gate dielectric material (4120, wherein the second gate structure (512); (514) comprises the gate dielectric material (512) along the second sidewalls of the second fin (408’) and along a second upper surface of the second fin (408’), and comprises a second gate electrode (514) over the gate dielectric material (512); and a dielectric structure (412); (312) between the first gate structure (414) and the second gate structure (512), wherein the dielectric structure (312) extends along and contacts a first sidewall of the first gate structure (414), and extends along and contacts a second sidewall of the second gate structure (514), wherein an upper portion of the dielectric structure (312) distal from the substrate (300) has a first width, and a lower portion of the dielectric structure (parts of (412) on (310); lower part of (312) )proximate to the substrate (300) has a second width larger than the first width (upper part of (312)).
Regarding claim 12, Tung discloses wherein a lower surface of the dielectric structure (312); (412) facing the substrate (300) is in contact with the dummy fin (310).
Regarding claim 13, Tung discloses wherein the lower surface of the dielectric structure (312); (412) is closer to the substrate (300) than a first upper surface of the first fin (408’) distal from the substrate (300).
Regarding claim 14, Tung discloses wherein an upper surface of the dielectric structure (312) distal from the substrate is level with an upper surface of the first gate structure (414) distal from the substrate (300).
Regarding claim 15, Tung discloses wherein the first width and the second width are measured along a first longitudinal direction of the first gate structure (414) (Fig.14).
Regarding claim 16, Tung discloses wherein a third width of the upper portion of the dielectric structure (312) is a same as a fourth width of the lower portion (304’’); (412) of the dielectric structure, wherein the third width and the fourth width are measured along a direction perpendicular to the first longitudinal direction and parallel to a major upper surface of the substrate (300).
Regarding claim 17, Tung discloses a semiconductor device comprising: a first fin (Fig.14, numeral 408’) over a substrate (300); a second fin (408’) over the substrate (300) and adjacent to the first fin (408’); a dummy fin (310) between the first fin (408’) and the second fin (408’); isolation regions (304’’) on opposing sides of the first fin (408’), on opposing sides of the second fin (408’), and on opposing sides of the dummy fin (310), wherein the first fin, the second fin, and dummy fin extend above the isolation regions (304’’), wherein the isolation regions (304’’) contact first sidewalls of the first fin (408’), second sidewalls of the second fin (408’), and third sidewalls of the dummy fin (310); a first gate structure (412); (414) over the first fin, wherein the first gate structure comprises a gate dielectric material (412) along the first sidewalls of the first fin (408’) and along a first upper surface of the first fin, and comprises a first gate electrode (414) over the gate dielectric material (412); a second gate structure (512); (514) over the second fin (408’) and adjacent to the first gate structure (414), wherein the second gate structure comprises the gate dielectric material (512) along the second sidewalls of the second fin (408’) and along a second upper surface of the second fin (408’), and comprises a second gate electrode (514) over the gate dielectric material (512), wherein a first longitudinal axis of the first gate structure (414) and a second longitudinal axis of the second gate structure (514) extend along a same line; and a dielectric structure (412); (312) interposed between and contacting the first gate structure (414) and the second gate structure (514), wherein in a cross-sectional view along the first longitudinal axis of the first gate structure, an upper portion of dielectric structure (312) distal from the substrate is narrower than a lower portion of the dielectric structure (312); (412) proximate to the substrate (300).
Regarding claim 18, Tung discloses wherein the dielectric structure (312); (412) extends from an upper surface of the first gate structure (414) distal from the substrate (300) to the dummy fin (310) (Fig.14).
Regarding claim 19, Tung discloses wherein the first fin (408’) and the second fin (408’) extend further from the substrate than the dummy fin (310) (Fig.14).
Claim(s) 17 and 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Huang (US 2019/0131428).
Regarding claim 17, Huang discloses a semiconductor device comprising: a first fin (Fig.11, numeral 106) over a substrate (102); a second fin (106) over the substrate (102) and adjacent to the first fin (106); a dummy fin (110) between the first fin (106) and the second fin (106); isolation regions (numerals (108); (127a); (127b)) on opposing sides of the first fin (106), on opposing sides of the second fin (106), and on opposing sides of the dummy fin (122), wherein the first fin (106), the second fin (106), and dummy fin (122) extend above the isolation regions (108), wherein the isolation regions (108) contact first sidewalls of the first fin (106), second sidewalls of the second fin (106), and third sidewalls of the dummy fin (110); a first gate structure (123a); (123b) over the first fin (106), wherein the first gate structure comprises a gate dielectric material (123a) along the first sidewalls of the first fin and along a first upper surface of the first fin (106), and comprises a first gate electrode (123b) over the gate dielectric material (123a); a second gate structure (123a); (123b) over the second fin (106) and adjacent to the first gate structure (123), wherein the second gate structure comprises the gate dielectric material (123a) along the second sidewalls of the second fin and along a second upper surface of the second fin, and comprises a second gate electrode (123b) over the gate dielectric material, wherein a first longitudinal axis of the first gate structure and a second longitudinal axis of the second gate structure extend along a same line (Fig.11); and a dielectric structure (122) interposed between and contacting the first gate structure (123b) and the second gate structure (123b), wherein in a cross-sectional view along the first longitudinal axis of the first gate structure, an upper portion of dielectric structure (122) distal from the substrate is narrower than a lower portion of the dielectric structure proximate to the substrate (102) (Fig. 11).
Regarding claim 20, Huang discloses a first gate spacer (Fig.11, 122a) on a first side of the first gate structure (123b); and a second gate spacer (122a) on a second side of the first gate structure (123B) opposing the first side ([0030]), wherein the dielectric structure (122) extends continuously from the first gate spacer (122a) to the second gate spacer (122a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung as applied to claim 1 above, and further in view of Danek (US 8, 685, 867).
Regarding claim 9, Tung does not disclose wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer around the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise a same dielectric material but have different material densities.
Tung however discloses that the dielectric structure is an interlayer dielectric layer ([0031]). And Danek discloses that the interlayer dielectric layer comprises a first dielectric material and a second dielectric material around the first dielectric material, wherein the first dielectric material and the second dielectric material comprise a same dielectric material but have different material densities (Abstract).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Danek to have the dielectric structure comprises a first dielectric material and a second dielectric material around the first dielectric material, wherein the first dielectric material and the second dielectric material comprise a same dielectric material but have different material densities for the purpose of effective filling of dielectric material into gaps (Danek, column 1, lines 30-35).
Conclusion
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/JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
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