DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/9/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 15 is objected to because of the following informalities:
In claim 15, line 2, the limitation of “tan” should be corrected into “than”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6-11, 16 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16-20 of U.S. Patent No. 12,080,602 in view of Hsieh (US 2017/0221907).
Regarding claim 1, Pat '602 discloses, in claim 16, a semiconductor device structure, comprising:
a substrate; a first fin structure, a second fin structure, and a third fin structure over the substrate; a first epitaxial structure extending across sidewalls of the first fin structure and the second fin structure; and a second epitaxial structure on the third fin structure, wherein the first epitaxial structure is closer to the substrate than the second epitaxial structure (all limitations are the same with the limitations recited in claim 16 of Pat '602).
Pat '602 does not explicitly disclose tops of the second fin structure and the third fin structure are at different height levels.
Hsieh teaches, in at least figure 13 and related text, the device comprising tops of the second fin structure (21, [43]) and the third fin structure (22, [43]) are at different height levels, for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Pat '602 and Hsieh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 with the specified features of Hsieh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 to have the tops of the second fin structure and the third fin structure being at different height levels, as taught by Hsieh, for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78], Hsieh).
Regarding claim 2, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Pat '602 further discloses, in claim 17, the first epitaxial structure is taller than the second epitaxial structure (all limitations are the same with the limitations recited in claim 17 of Pat '602).
Regarding claim 3, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Pat '602 further discloses, in claim 18, a first spacer element below and in direct contact with the first epitaxial structure; and a second spacer element below and in direct contact with the second epitaxial structure (all limitations are the same with the limitations recited in claim 18 of Pat '602).
Regarding claim 4, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 3 as described above.
Pat '602 further discloses, in claim 19, the second spacer element is taller than the first spacer element (all limitations are the same with the limitations recited in claim 19 of Pat '602).
Regarding claim 6, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Pat '602 further discloses, in claim 20, the first epitaxial structure is wider than the second epitaxial structure (all limitations are the same with the limitations recited in claim 20 of Pat '602).
Regarding claim 7, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Hsieh further teaches, in at least figure 13 and related text, an isolation feature (30, [45]) laterally surrounding the first fin structure (20, [43]), the second fin structure (21, [43]), and the third fin structure (22, [43]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 8, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 7 as described above.
Hsieh further teaches, in at least figure 13 and related text, the first epitaxial structure (63, [56]) is in direct contact with the isolation feature (30, [45]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 9, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 7 as described above.
Hsieh further teaches, in at least figure 13 and related text, a top of the isolation feature (30, [45]) and the tops of the second fin structure (21, [43]) and the third fin structure (22, [43]) are at different height levels, for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 10, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 7 as described above.
Hsieh further teaches, in at least figure 13 and related text, a top of the first fin structure (20, [43]) is closer to the substrate (10, [36]) than a top of the isolation feature (30, [45]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 11, Pat '602 discloses, in claims 16 and 17, a semiconductor device structure, comprising:
a substrate; a first fin structure, a second fin structure, and a third fin structure over the substrate; and a second epitaxial structure on the third fin structure (all limitations are the same with the limitations recited in claim 16 of Pat '602), wherein the first epitaxial structure is taller than the second epitaxial structure (all limitations are the same with the limitations recited in claim 17 of Pat '602).
Pat '602 does not explicitly disclose tops of the first fin structure and the second fin structure are closer to the substrate than a top of the third fin structure; a first epitaxial structure extending across opposite sidewalls of the first fin structure and opposite sidewalls of the second fin structure.
Hsieh teaches, in at least figure 13 and related text, the device comprising tops of the first fin structure (20, [43]) and the second fin structure (21, [43]) are closer to the substrate (10, [36]) than a top of the third fin structure (22, [43]); a first epitaxial structure (63, [56]) extending across opposite sidewalls of the first fin structure (20, [43]) and opposite sidewalls of the second fin structure (21, [43]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Pat '602 and Hsieh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 with the specified features of Hsieh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 to have the tops of the first fin structure and the second fin structure are closer to the substrate than a top of the third fin structure; the first epitaxial structure extending across opposite sidewalls of the first fin structure and opposite sidewalls of the second fin structure, as taught by Hsieh, for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78], Hsieh).
Regarding claim 16, Pat '602 discloses, in claims 16 and 17, a semiconductor device structure, comprising:
a substrate; a first fin structure, a second fin structure, and a third fin structure over the substrate; and a second epitaxial structure on the third fin structure (all limitations are the same with the limitations recited in claim 16 of Pat '602).
Pat '602 does not explicitly disclose the third fin structure is taller than each of the first fin structure and the second fin structure; a first epitaxial structure connecting the first fin structure and the second fin structure; bottoms of the first epitaxial structure and the second epitaxial structure are at different height levels.
Hsieh teaches, in at least figure 13 and related text, the device comprising the third fin structure (22, [43]) is taller than each of the first fin structure (20, [43]) and the second fin structure (21, [43]); a first epitaxial structure (63, [56]) connecting the first fin structure (20, [43]) and the second fin structure (21, [43]); bottoms of the first epitaxial structure (63, [56]) and the second epitaxial structure (72, [61]) are at different height levels, for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Pat '602 and Hsieh are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 with the specified features of Hsieh because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 to have the third fin structure being taller than each of the first fin structure and the second fin structure; the first epitaxial structure connecting the first fin structure and the second fin structure; the bottoms of the first epitaxial structure and the second epitaxial structure being at different height levels, as taught by Hsieh, for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78], Hsieh).
Regarding claim 20, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 16 as described above.
Hsieh further teaches, in at least figure 13 and related text, an isolation feature (30, [45]) laterally surrounding the first fin structure (20, [43]), the second fin structure (21, [43]), and the third fin structure (22, [43]), wherein the third fin structure (22, [43]) protrudes from a top surface of the isolation feature (30, [45]), and a top of the first fin structure (20, [43]) is closer to the substrate (10, [36]) than the top surface of the isolation feature (30, [45]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Claims 5, 12-15 and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16-20 of U.S. Patent No. 12,080,602 in view of Hsieh (US 2017/0221907), and further in view of Holt (US 2018/0374759).
Regarding claim 5, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 3 as described above.
Pat '602 in view of Hsieh does not explicitly disclose the first epitaxial structure has a first lower surface above a top of the first spacer element, the second epitaxial structure has a second lower surface above a top of the second spacer element, and the first lower surface is closer to the substrate than the second lower surface.
Holt teaches, in at least figure 7 and related text, the device comprising the first epitaxial structure (124, [29]) has a first lower surface above a top of the first spacer element (114 of 106, [29]), the second epitaxial structure (126, [30]) has a second lower surface above a top of the second spacer element (114 of 110, [30]), and the first lower surface is closer to the substrate (102, [19]) than the second lower surface, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Pat '602, Hsieh, and Holt are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 in view of Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 in view of Hsieh to have the first epitaxial structure having a first lower surface above a top of the first spacer element, the second epitaxial structure having a second lower surface above a top of the second spacer element, and the first lower surface being closer to the substrate than the second lower surface, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 12, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 11 as described above.
Hsieh further teaches, in at least figure 13 and related text, an isolation feature (30, [45]) laterally surrounding the first fin structure (20, [43]), the second fin structure (21, [43]), and the third fin structure (22, [43]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Pat '602 in view of Hsieh does not explicitly disclose the second epitaxial structure is spaced apart from the isolation feature.
Holt teaches, in at least figure 7 and related text, the device comprising the second epitaxial structure (126, [30]) is spaced apart from the isolation feature (112, [22]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Pat '602, Hsieh, and Holt are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 in view of Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 in view of Hsieh to have the second epitaxial structure being spaced apart from the isolation feature, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 13, Pat '602 in view of Hsieh and Holt discloses the semiconductor device structure as claimed in claim 12 as described above.
Hsieh further teaches, in at least figure 13 and related text, the first epitaxial structure (63, [56]) is in direct contact with the isolation feature (30, [45]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 14, Pat '602 in view of Hsieh and Holt discloses the semiconductor device structure as claimed in claim 12 as described above.
Hsieh further teaches, in at least figure 13 and related text, the tops of the first fin structure (20, [43]) and the second fin structure (21, [43]) are closer to the substrate (10, [36]) than a top of the isolation feature (30, [45]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 15, Pat '602 in view of Hsieh and Holt discloses the semiconductor device structure as claimed in claim 12 as described above.
Hsieh further teaches, in at least figure 13 and related text, a top of the isolation feature (30, [45]) is closer to the substrate (10, [36]) tan the top of the third fin structure (22, [43]), for the purpose of increasing a contact area between the epitaxial S/D structure and a bar contact ([78]).
Regarding claim 17, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 16 as described above.
Pat '602 in view of Hsieh does not explicitly disclose a spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure.
Holt teaches, in at least figure 7 and related text, the device comprising a spacer element (114 of 110, [22]) in direct contact with an interface between the third fin structure (108, [22]) and the second epitaxial structure (126, [30]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Pat '602, Hsieh, and Holt are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 in view of Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 in view of Hsieh to have the spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 18, Pat '602 in view of Hsieh discloses the semiconductor device structure as claimed in claim 16 as described above.
Pat '602 further discloses, in claim 18, a first spacer element in direct contact with the first epitaxial structure ("a first spacer element below and in direct contact with the first epitaxial structure", in claim 18 of Pat '602, is interpreted as the same limitation).
Pat '602 in view of Hsieh does not explicitly disclose a second spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure.
Holt teaches, in at least figure 7 and related text, the device comprising a second spacer element (114 of 110, [22]) in direct contact with an interface between the third fin structure (108, [22]) and the second epitaxial structure (126, [30]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Pat '602, Hsieh, and Holt are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '602 in view of Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '602 in view of Hsieh to have the second spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 19, Pat '602 in view of Hsieh and Holt discloses the semiconductor device structure as claimed in claim 18 as described above.
Pat '602 further discloses, in claim 19, the second spacer element is taller than the first spacer element (all limitations are the same with the limitations recited in claim 19 of Pat '602).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1- is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hsieh (US 2017/0221907).
Regarding claim 1, Hsieh discloses, in at least figure 13 and related text, a semiconductor device structure, comprising:
a substrate (10, [36]);
a first fin structure (20, [43]), a second fin structure (21, [43]), and a third fin structure (22, [43]) over the substrate (10, [36]), wherein tops of the second fin structure (21, [43]) and the third fin structure (22, [43]) are at different height levels;
a first epitaxial structure (63, [56]) extending across sidewalls of the first fin structure (20, [43]) and the second fin structure (21, [43]); and
a second epitaxial structure (72, [61]) on the third fin structure (22, [43]), wherein the first epitaxial structure (63, [56]) is closer to the substrate (10, [36]) than the second epitaxial structure (72, [61]).
Regarding claim 2, Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Hsieh further discloses, in at least figure 13 and related text, the first epitaxial structure (63, [56]) is taller than the second epitaxial structure (72, [61]).
Regarding claim 6, Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Hsieh further discloses, in at least figure 13 and related text, the first epitaxial structure (63, [56]) is wider than the second epitaxial structure (72, [61]).
Regarding claim 7, Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Hsieh further discloses, in at least figure 13 and related text, an isolation feature (30, [45]) laterally surrounding the first fin structure (20, [43]), the second fin structure (21, [43]), and the third fin structure (22, [43]).
Regarding claim 8, Hsieh discloses the semiconductor device structure as claimed in claim 7 as described above.
Hsieh further discloses, in at least figure 13 and related text, the first epitaxial structure (63, [56]) is in direct contact with the isolation feature (30, [45]).
Regarding claim 9, Hsieh discloses the semiconductor device structure as claimed in claim 7 as described above.
Hsieh further discloses, in at least figure 13 and related text, a top of the isolation feature (30, [45]) and the tops of the second fin structure (21, [43]) and the third fin structure (22, [43]) are at different height levels.
Regarding claim 10, Hsieh discloses the semiconductor device structure as claimed in claim 7 as described above.
Hsieh further discloses, in at least figure 13 and related text, a top of the first fin structure (20, [43]) is closer to the substrate (10, [36]) than a top of the isolation feature (30, [45]).
Regarding claim 11, Hsieh discloses, in at least figure 13 and related text, a semiconductor device structure, comprising:
a substrate (10, [36]);
a first fin structure (20, [43]), a second fin structure (21, [43]), and a third fin structure (22, [43]) over the substrate (10, [36]), wherein tops of the first fin structure (20, [43]) and the second fin structure (21, [43]) are closer to the substrate (10, [36]) than a top of the third fin structure (22, [43]);
a first epitaxial structure (63, [56]) extending across opposite sidewalls of the first fin structure (20, [43]) and opposite sidewalls of the second fin structure (21, [43]); and
a second epitaxial structure (72, [61]) on the third fin structure (22, [43]), wherein the first epitaxial structure (63, [56]) is taller than the second epitaxial structure (72, [61]).
Regarding claim 16, Hsieh discloses, in at least figure 13 and related text, a semiconductor device structure, comprising:
a substrate (10, [36]);
a first fin structure (20, [43]), a second fin structure (21, [43]), and a third fin structure (22, [43]) over the substrate (10, [36]), wherein the third fin structure (22, [43]) is taller than each of the first fin structure (20, [43]) and the second fin structure (21, [43]);
a first epitaxial structure (63, [56]) connecting the first fin structure (20, [43]) and the second fin structure (21, [43]); and
a second epitaxial structure (72, [61]) on the third fin structure (22, [43]), wherein bottoms of the first epitaxial structure (63, [56]) and the second epitaxial structure (72, [61]) are at different height levels.
Regarding claim 20, Hsieh discloses the semiconductor device structure as claimed in claim 16 as described above.
Hsieh further discloses, in at least figure 13 and related text, an isolation feature (30, [45]) laterally surrounding the first fin structure (20, [43]), the second fin structure (21, [43]), and the third fin structure (22, [43]), wherein the third fin structure (22, [43]) protrudes from a top surface of the isolation feature (30, [45]), and a top of the first fin structure (20, [43]) is closer to the substrate (10, [36]) than the top surface of the isolation feature (30, [45]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5, 12-15 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh (US 2017/0221907) in view of Holt (US 2018/0374759).
Regarding claim 3, Hsieh discloses the semiconductor device structure as claimed in claim 1 as described above.
Hsieh does not explicitly disclose a first spacer element below and in direct contact with the first epitaxial structure; a second spacer element below and in direct contact with the second epitaxial structure.
Holt teaches, in at least figure 7 and related text, the device comprising a first spacer element (114 of 106, [29]) below and in direct contact with the first epitaxial structure (124, [29]); a second spacer element (114 of 106, [29]) below and in direct contact with the second epitaxial structure (126, [30]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Hsieh and Holt are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsieh to have the first spacer element below and in direct contact with the first epitaxial structure; the second spacer element below and in direct contact with the second epitaxial structure, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 5, Hsieh discloses the semiconductor device structure as claimed in claim 3 as described above.
Holt further teaches, in at least figure 7 and related text, the first epitaxial structure (124, [29]) has a first lower surface above a top of the first spacer element (114 of 106, [29]), the second epitaxial structure (126, [30]) has a second lower surface above a top of the second spacer element (114 of 110, [30]), and the first lower surface is closer to the substrate (102, [19]) than the second lower surface, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Regarding claim 12, Hsieh discloses the semiconductor device structure as claimed in claim 11 as described above.
Hsieh further discloses, in at least figure 13 and related text, an isolation feature (30, [45]) laterally surrounding the first fin structure (20, [43]), the second fin structure (21, [43]), and the third fin structure (22, [43]).
Hsieh does not explicitly disclose the second epitaxial structure is spaced apart from the isolation feature.
Holt teaches, in at least figure 7 and related text, the device comprising the second epitaxial structure (126, [30]) is spaced apart from the isolation feature (112, [22]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Hsieh and Holt are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsieh to have the second epitaxial structure being spaced apart from the isolation feature, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 13, Hsieh in view of Holt discloses the semiconductor device structure as claimed in claim 12 as described above.
Hsieh further discloses, in at least figure 13 and related text, the first epitaxial structure (63, [56]) is in direct contact with the isolation feature (30, [45]).
Regarding claim 14, Hsieh in view of Holt discloses the semiconductor device structure as claimed in claim 12 as described above.
Hsieh further discloses, in at least figure 13 and related text, the tops of the first fin structure (20, [43]) and the second fin structure (21, [43]) are closer to the substrate (10, [36]) than a top of the isolation feature (30, [45]).
Regarding claim 15, Hsieh in view of Holt discloses the semiconductor device structure as claimed in claim 12 as described above.
Hsieh further discloses, in at least figure 13 and related text, a top of the isolation feature (30, [45]) is closer to the substrate (10, [36]) tan the top of the third fin structure (22, [43]).
Regarding claim 17, Hsieh discloses the semiconductor device structure as claimed in claim 16 as described above.
Hsieh does not explicitly disclose a spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure.
Holt teaches, in at least figure 7 and related text, the device comprising a spacer element (114 of 110, [22]) in direct contact with an interface between the third fin structure (108, [22]) and the second epitaxial structure (126, [30]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Hsieh and Holt are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsieh to have the spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Regarding claim 18, Hsieh discloses the semiconductor device structure as claimed in claim 16 as described above.
Hsieh does not explicitly disclose a first spacer element in direct contact with the first epitaxial structure; a second spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure.
Holt teaches, in at least figure 7 and related text, the device comprising a first spacer element (114 of 106, [29]) in direct contact with the first epitaxial structure (124, [29]); a second spacer element (114 of 110, [22]) in direct contact with an interface between the third fin structure (108, [22]) and the second epitaxial structure (126, [30]), for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15]).
Hsieh and Holt are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh with the specified features of Holt because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Hsieh to have the first spacer element in direct contact with the first epitaxial structure; the second spacer element in direct contact with an interface between the third fin structure and the second epitaxial structure, as taught by Holt, for the purpose of providing a physical boundary in the form of a blocking layer between fin structures of adjacent devices ([15], Holt).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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