DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12062652 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are a broader representation of claims disclosed in US 12,062,652 B2 .
US 12,062,652
Application 18/767,239
1. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of first interconnect layers each having a length extending in a first direction and arranged along a second direction transverse to the first direction; forming a single piece of first resistive layer over the first interconnect layers; forming a dielectric layer over the first resistive layer; forming a second resistive layer over the dielectric layer; forming a plurality of second interconnect layers each having a length extending in the second direction and arranged along the first direction; and forming a plurality of vias interconnecting the second interconnect layers and the second resistive layer, each via having a length extending in a third direction transverse to the first and second directions.
1. A method for manufacturing a semiconductor device, the method comprising: forming a first resistive layer; forming a second resistive layer over the first resistive layer; forming a plurality of first interconnect layers each having a length extending in a first direction and arranged along a second direction; and forming a plurality of vias interconnecting the first interconnect layers and the second resistive layer, each via having a length extending in a third direction transverse to the first and second directions.
9. A semiconductor device comprising: a plurality of first interconnect layers each having a length extending in a first direction and arranged along a second direction transverse to the first direction; a single piece of first resistive layer over the first interconnect layers; a dielectric layer over the first resistive layer; a second resistive layer over the dielectric layer; a plurality of second interconnect layers each having a length extending in the second direction and arranged along the first direction; and a plurality of vias interconnecting the second interconnect layers and the second resistive layer, each via having a length extending in a third direction transverse to the first and second directions.
9. A semiconductor device comprising: a first resistive layer; a second resistive layer over the first resistive layer; a plurality of first interconnect layers each having a length extending in a first direction and arranged along a second direction; and a plurality of vias interconnecting the first interconnect layers and the second resistive layer, each via having a length extending in a third direction transverse to the first and second directions.
16. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of first interconnect layers each having a length extending in a first direction and arranged in a second direction transverse to the first direction; forming a single piece of first resistive layer over the first interconnect layers; forming a dielectric layer over the first resistive layer; forming a second resistive layer over the dielectric layer, wherein the first resistive layer, the dielectric layer, and the second resistive layer are formed using a single mask; forming a plurality of second interconnect layers each having a length extending in the second direction and arranged along the first direction; and forming a plurality of vias interconnecting the second interconnect layers and the second resistive layer, each via having a length extending in a third direction transverse to the first and second directions.
16. A method for manufacturing a semiconductor device, the method comprising: forming a first resistive layer; forming a second resistive layer over the first resistive layer, wherein the first and second resistive layers are formed using a single mask; forming a plurality of first interconnect layers each having a length extending in a first direction and arranged along a second direction; and forming a plurality of vias interconnecting the first interconnect layers and the second resistive layer, each via having a length extending in a third direction transverse to the first and second directions.
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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