Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 10 and 18
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 12/18/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12,080,375 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’375 as shown below in Table format, we find that they both recite the same claim limitations.
Instant Application
US 12,080,375 B2
1. A circuit, comprising: a first branch comprising a first transistor, a first memory bit cell, and a first clamping transistor coupled to the first memory bit cell; a second branch comprising a second transistor, a second memory bit cell, and a second clamping transistor coupled to the second memory bit cell; a first plurality of trimming transistors coupled to the first transistor, wherein each of the first plurality of trimming transistors is configured to be selectively turned on to reduce a first level of current flowing through the first branch; and a second plurality of trimming transistors coupled to the second transistor, wherein each of the second plurality of trimming transistors is configured to be selectively turned on to reduce a second level of current flowing through the second branch.
1. A circuit, comprising: a first branch comprising a first plurality of transistors, a first memory bit cell, a first clamping transistor coupled to the first memory bit cell; a second branch comprising a second plurality of transistors, a second memory bit cell, a second clamping transistor coupled to the second memory bit cell; a first plurality of trimming transistors that are connected in parallel to each other and connected in parallel to at least one of the first plurality of transistors; and a second plurality of trimming transistors that are connected in parallel to each other and connected in parallel to at least one of the second plurality of transistors.
2. The circuit of claim 1, wherein: each of the first plurality of trimming transistors is capable of being selectively turned on to reduce a first signal level of current flowing through the first branch; and each of the second plurality of trimming transistors is capable of being selectively turned on to reduce a second signal level of current flowing through the second branch.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,783,873 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’873 we find that they both recite the same claim limitations.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,373,690 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’690 we find that they both recite the same claim limitations.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,957,366 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’366 we find that they both recite the same claim limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over DeBrosse et al. (US 7239537).
Regarding independent claim 1, DeBrosse discloses a circuit (Figs. 1-3), comprising:
a first branch comprising a first transistor, a first memory bit cell, and a first clamping transistor coupled to the first memory bit cell (Figs. 1-2 show leftmost vertical branch BL/INPUTA with a transistor T5, memory cell 108 and clamp transistor T1);
a second branch comprising a second transistor, a second memory bit cell, and a second clamping transistor coupled to the second memory bit cell (Figs. 1-2 show rightmost vertical branch refBL1/INPUTB with a transistor T6, memory cell 110a and clamp transistor T2);
a first plurality of trimming transistors coupled to the first transistor (Fig. 2 and (14) describes a first plurality of trim transistors 202 in first branch), wherein each of the first plurality of trimming transistors is configured to be selectively turned on to reduce a first level of current flowing through the first branch ((11) and (12) describes that first and second plurality of trim transistors is individually activated so as to compensate for a determined device mismatch with respect to the data and reference sides of the sense amplifier); and
a second plurality of trimming transistors coupled to the second transistor (Fig. 2 and (14) describes a second plurality of trim transistors 204 in second branch), wherein each of the second plurality of trimming transistors is configured to be selectively turned on to reduce a second level of current flowing through the second branch ((11) and (12) describes that first and second plurality of trim transistors is individually activated so as to compensate for a determined device mismatch with respect to the data and reference sides of the sense amplifier).
Regarding claim 2, DeBrosse discloses all the elements of claim 1 as above and further each of the first plurality of trimming transistors is connected in parallel to each other and connected in parallel to the first transistor; and each of the second plurality of trimming transistors is connected in parallel to each other and connected in parallel to the second transistor (Fig. 2 shows parallel inter-connection of trimming transistors 202 and also with transistor T5 and similarly parallel inter-connection of trimming transistors 204 and also with transistor T6.
Regarding claim 3, DeBrosse discloses all the elements of claim 1 as above and further each of the first plurality of trimming transistors, when being individually turned on, reduces the first level of current flowing through the first branch by a first percentage; and each of the second plurality of trimming transistors, when being individually turned on, reduces the second level of current flowing through the second branch by a second percentage (Fig. 2 and (16)-(17) describes how each trim transistor TL (on left side) and TR (on right side) being activated (conductive state) and controls the current flow).
Regarding claim 4, DeBrosse discloses all the elements of claim 3 as above and further the first plurality of trimming transistors comprises a first number of turned-on trimming transistors configured to reduce the first level of current flowing through the first branch to compensate a mismatch between currents flowing through the first branch and the second branch (Fig. 2 and (18) describes in order to compensate for an offset due to a sense amplifier device mismatch, the number of activated trim transistors on the data side (for example) of the sense amplifier can be reduced such that 0.ltoreq.NL<NR in order to reduce the effective width of T.sub.5 compared to T.sub.6. On the other hand, in order to increase the effective width of T.sub.5 compared to T.sub.6, more trim transistors on the data side can be activated with respect to those on the reference side such that 0.ltoreq.NR<NL. In either instance, by adjusting the effective widths of the load transistors T.sub.5, T.sub.6, with respect to one another, compensation for positive or negative offsets may be achieved).
Regarding claim 5, DeBrosse discloses all the elements of claim 4 as above and regarding: the mismatch indicates a stronger current flowing through the first branch than that flowing through the second branch; and the first number is determined based on the first percentage and the mismatch; even though DeBrosse does not explicitly teach calculating a first number based on the first percentage and the mismatch, DeBrosse suggested calculating the number of activated trim transistors in order to compensate for an offset due to a mismatch and similar mathematical formula (Fig. 2 along with((18)).
Regarding claim 6, DeBrosse discloses all the elements of claim 3 as above and further the second plurality of trimming transistors comprises a second number of turned-on trimming transistors configured to reduce the second level of current flowing through the second branch to compensate a mismatch between currents flowing through the first branch and the second branch (Fig. 2 and (18)).
Regarding claim 7, DeBrosse discloses all the elements of claim 6 as above and regarding: the mismatch indicates a stronger current flowing through the second branch than that flowing through the first branch; and the second number is determined based on the second percentage and the mismatch even though DeBrosse does not explicitly teach calculating a first number based on the first percentage and the mismatch, DeBrosse suggested calculating the number of activated trim transistors in order to compensate for an offset due to a mismatch and similar mathematical formula (Fig. 2 along with((18)).
Regarding claim 8, DeBrosse discloses all the elements of claim 2 as above and further the first level of current is configured to serve as a cell signal for a sense amplifier, and the second level of current is configured to serve as a reference signal for the sense amplifier (Figs. 1-2 shows first branch for cell signal and second branch for reference signal for the sense amplifier) .
Regarding independent claim 10, DeBrosse discloses a circuit (Figs. 1-3), comprising:
a first memory bit cell (Fig. 1 shows memory cell 108);
a second memory bit cell (Fig. 1 shows memory cell 110a);
a first branch comprising a first clamping transistor coupled to the first memory bit cell (Fig. 2 shows transistor T5 along first branch INPUTA connected to memory cell);
a second branch comprising a second clamping transistor coupled to the second memory bit cell (Fig. 2 shows transistor T6 along second branch INPUTB connected to memory cell);
Remaining part of claim 10 is exactly the same as claim 1 and henceforth rejected the same way.
Claims 11-15 recite the same limitation of claims 2-7 and henceforth rejected the same way.
Regarding claim 16, DeBrosse discloses all the elements of claim 10 as above and further the first branch further comprises a first transistor and a second transistor (Fig. 1 shows transistor T1 and a column select transistor from block 104 along the first branch);
the first node is coupled between the first transistor and the second transistor (Fig. 1 shows there is a node in-between);
the second branch further comprises a third transistor and a fourth transistor (Fig. 1 shows transistor T2 and another column select transistor from block 104 along the second branch); and
the second node is coupled between the third transistor and the fourth transistor (Fig. 1 shows there is another node in-between).
Claim 17 recites the same limitation of claim 8 and henceforth rejected the same way.
Independent claim 18 recites the same limitation of independent claim 1 in method format and henceforth rejected the same way.
Claim 19 recites the same limitation of claims 3 and 5 together in method format and henceforth rejected the same way.
Claim 20 recites the same limitation of claim 17 in method format and henceforth rejected the same way.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Maffitt et al. (US 10726897) --- Abstract and whole Specification discloses the same inventive concept.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 12/26/2025