Prosecution Insights
Last updated: August 17, 2026
Application No. 18/767,858

CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER

Final Rejection §DP
Filed
Jul 09, 2024
Priority
May 24, 2018 — provisional 62/675,947 +4 more
Examiner
BEGUM, SULTANA
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
510 granted / 546 resolved
+25.4% vs TC avg
Minimal +0% lift
Without
With
+0.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
17 currently pending
Career history
571
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of claim(s) to be treated in this office action: a. Independent: 1, 10 and 18 b. Pending: 1-20 Claims 18 and 19 have been amended. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12,080,375 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’375 as shown below in Table format, we find that they both recite the same claim limitations. Instant Application US 12,080,375 B2 1. A circuit, comprising: a first branch comprising a first transistor, a first memory bit cell, and a first clamping transistor coupled to the first memory bit cell; a second branch comprising a second transistor, a second memory bit cell, and a second clamping transistor coupled to the second memory bit cell; a first plurality of trimming transistors coupled to the first transistor, wherein each of the first plurality of trimming transistors is configured to be selectively turned on to reduce a first level of current flowing through the first branch; and a second plurality of trimming transistors coupled to the second transistor, wherein each of the second plurality of trimming transistors is configured to be selectively turned on to reduce a second level of current flowing through the second branch. 1. A circuit, comprising: a first branch comprising a first plurality of transistors, a first memory bit cell, a first clamping transistor coupled to the first memory bit cell; a second branch comprising a second plurality of transistors, a second memory bit cell, a second clamping transistor coupled to the second memory bit cell; a first plurality of trimming transistors that are connected in parallel to each other and connected in parallel to at least one of the first plurality of transistors; and a second plurality of trimming transistors that are connected in parallel to each other and connected in parallel to at least one of the second plurality of transistors. 2. The circuit of claim 1, wherein: each of the first plurality of trimming transistors is capable of being selectively turned on to reduce a first signal level of current flowing through the first branch; and each of the second plurality of trimming transistors is capable of being selectively turned on to reduce a second signal level of current flowing through the second branch. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,783,873 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’873 we find that they both recite the same claim limitations. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,373,690 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’690 we find that they both recite the same claim limitations. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,957,366 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare claim 1 of Instant Application with claim 1 and 2 of US Patent ’366 we find that they both recite the same claim limitations. Response to Arguments Applicant’s arguments, see Remarks, filed 5/29/2026, with respect to 103 Rejection have been fully considered and are persuasive. 103 Rejection have been withdrawn. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SULTANA BEGUM/Primary Examiner, Art Unit 2824 7/17/2026
Read full office action

Prosecution Timeline

Jul 09, 2024
Application Filed
Dec 30, 2025
Non-Final Rejection mailed — §DP
May 29, 2026
Response Filed
Jul 22, 2026
Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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ENHANCED VALLEY TRACKING WITH TRIM SETTING UPDATES IN A MEMORY DEVICE
2y 9m to grant Granted Jun 23, 2026
Patent 12658234
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3y 10m to grant Granted Jun 16, 2026
Patent 12658235
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3y 1m to grant Granted Jun 16, 2026
Patent 12658222
MEMORY DEVICE AND OPERATING METHOD WITH TEMPERATURE COMPENSATION CIRCUIT
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Patent 12658258
EVEN/ODD WORD LINE DRIVING IN 3D MEMORY
2y 7m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
94%
With Interview (+0.5%)
1y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allowance rate.

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