DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/10/2024 and 05/28/2026 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities:
Line 4 of claim 1 recites “ a passivation layer disposed on the metal features 106”.
Line 11 of claim 11 recites “a first bonding recess 122 formed in a top surface of the landing region and that overlaps with the contact region in a vertical direction”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-13 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11,728,301 in view of Yang (US 2019/0131277) for the following reasons:
Regarding claim 1 of the pending application, US Patent teaches a first die (col. 14, line 8) comprising:
a semiconductor substrate (col. 14, line 9);
a first interconnect structure (col. 14, line 10) disposed on the semiconductor substrate;
a passivation layer (refer to passivation layer on col. 14, line 12) disposed on the first interconnect structure (refer to first interconnect structure); and
a test pad disposed on the passivation layer (see col. 14 line 14), the test pad comprising:
a test region (see claim 7);
a landing region that extends from test region in a first horizontal direction (see claim 7);
a contact region that electrically connects a bottom surface of the landing region to one of the metal features (see col. 14, lines 15-17); and
a bonding recess formed in a top surface of the landing region and that overlaps with the contact region in a vertical direction (see col. 14, lines 17-20).
US Patent does not explicitly mention the interconnect structure comprising: metal features
Yang teaches the same field of an endeavor wherein Fig. 2 shows the interconnect structure comprising: metal features (refer to 204).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include metal features as the interconnect structure as taught by Yang in the teaching of US Patent so that the metal features of the interconnect structure provide electrical connect the different electrode regions and route signal.
Regarding claim 2 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding recess is configured to receive a bonding pad structure that is configured to electrically connect the first die to another die (see claim 1, col. 14, lines 23-25).
Regarding claim 3 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches a bonding pad structure directly contacting at least a portion of the bonding recess and configured to electrically connect the first die to another die (see claim 1, col. 14, lines 23-25).
Regarding claim 4 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding pad structure directly contacts from 0.1% to 100% of the bonding recess (see claim 2).
Regarding claim 5 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding pad structure directly contacts from 50% to 100% of the bonding recess (see claim 3).
Regarding claim 6 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding pad structure comprises: a bonding via structure that directly contacts the bonding recess; and a bonding pad that is disposed on the bonding via structure and is electrically connected to the second die (see claim 4).
Regarding claim 7 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding recess has a concave surface and is configured to decrease electrical contact resistance between the test pad and the bonding pad structure (see claim 11).
Regarding claim 8 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the test pad is formed of a material having a higher electrical resistance than a material used to form the bonding pad structure (see claim 9).
Regarding claim 9 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the test pad is formed of a material having a higher electrical resistance than a material used to form the bonding pad structure (see claim 8).
Regarding claim 10 of the pending application, US Patent teaches a semiconductor package (see claim 13’s preamble) comprising:
a first die (see col. 15, line 8) comprising:
a first semiconductor substrate (see col. 15, line 9);
a first interconnect structure disposed on the first semiconductor substrate (col. 15, lines 10-11);
a passivation layer disposed on the first interconnect structure (see col. 15, line 13); and
a test pad disposed on the passivation layer (see col 15, lines 14-15), the test pad comprising:
a contact region that electrically connects a bottom surface of the landing region to one of the metal features (see col. 15, lines 15-17); and
a bonding recess formed in a top surface of the landing region and that overlaps with the contact region in a vertical direction (see col. 15, lines 17-20);
a second die disposed on the first die (see col. 15, lines 21-22) and comprising
a second test pad (see col. 15, lines 28-29); and
a bonding pad structure that electrically connects the first bonding recess to a second bonding recess of the second test pad (see col. 35-38).
US Patent does not explicitly mention the interconnect structure comprising: metal features; and the test pad comprising: a first test region; and a landing region that extends from test region in a first horizontal direction.
Yang teaches the same field of an endeavor wherein Fig. 2 shows the interconnect structure comprising: metal features (refer to 204); and the test pad comprising: a first test region; and a landing region that extends from test region in a first horizontal direction (see notation below).
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Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include metal features as the interconnect structure and the test pad comprising: a first test region; and a landing region that extends from test region in a first horizontal direction as taught by Yang in the teaching of US Patent so that the metal features of the interconnect structure provide electrical connect the different electrode regions and route signal and the test region and the horizontal portion of the test pad are to provide a larger footprint and controlled overlap rather than requiring the probe contact area itself to sit directly over the interconnect.
Regarding claim 11 of the pending application, US Patent and Yang teaches all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding pad structure directly contacts from 0.1% to 100% of the bonding recess (see claim 14).
Regarding claim 12 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding pad structure comprises: a bonding via structure that directly contacts the first bonding recess; and a bonding pad that is disposed on the bonding via structure and is electrically connected to the second die (see claim 15).
Regarding claim 13 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches a die bonding structure comprising: a first bonding layer that covers the first die; and a second bonding layer that covers the second die and is bonded to the first bonding layer (see claim 16).
Regarding claim 16 of the pending application, US Patent and Yang teach all the limitations for the same reasons as set forth above. Besides, US Patent teaches the second die comprises: a second semiconductor substrate; a second interconnect structure disposed on the second semiconductor substrate; and a second passivation layer disposed on the second interconnect structure and under the second test pad, wherein the second test pad comprises a second contact region that extends through the second passivation layer and electrically contacts the second interconnect structure, and a second bonding recess that overlaps with the second contact region in the vertical direction (see claim 13, col. 14, lines 23-34).
Claims 17 and 18- 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 8 and 11 of U.S. Patent No. 11,728,301. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 17 of the pending application, US Patent teaches a first die (see claim 1’s preamble) comprising:
semiconductor devices (refer to first die and a second die as claimed in claim 1);
an interconnect structure (refer to a first interconnect structure) configured to electrically connect the semiconductor devices (refer to the first die and the second die as claimed in claim 1); and
a test pad disposed on the interconnect structure (see col. 14, lines 12- 14), the test pad comprising:
a contact region that is electrically connected to the interconnect structure (claim 1, col. 14, line 15);
a test region (claim 7); and
a bonding recess that overlaps with the contact region (see claim 1, col. 14, lines 16-17).
Regarding claim 18 of the pending application, US Patent teaches all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding recess is configured to receive a bonding pad structure that is configured to electrically connect the first die to another die (see claim 1).
Regarding claim 19 of the pending application, US Patent teaches all the limitations for the same reasons as set forth above. Besides, US Patent teaches the bonding recess has a concave surface and is configured to decrease electrical contact resistance between the test pad and a bonding pad structure configured to connect the first die to another die (see claim 11).
Regarding claim 20 of the pending application, US Patent teaches all the limitations for the same reasons as set forth above. Besides, US Patent teaches the test region is wider than the landing region and is configured to contact a test probe (see claim 8).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 20190131277).
Regarding claim 17, Yang teaches a first die in fig. 1A-D comprising:
semiconductor devices (100 and 200);
an interconnect structure (204/215 and 104/115) configured to electrically connect the semiconductor devices (100/200); and
a test pad (112) disposed on the interconnect structure (108b), the test pad comprising:
a contact region (refer to contact region where it is connected to the metal features 108b) that is electrically connected to the interconnect structure;
a test region (refer to test region 114b); and
a bonding recess that overlaps with the contact region.
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Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the bonding via structure extends through the first bonding layer and an interconnect planarization layer; and the bonding pad extends through the second bonding layer and contacts a second interconnect structure of the second die” in combination of all of the limitations of claim 14. Claim 15 includes all the limitations of claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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