DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Acknowledgment is made of applicant's Preliminary Amendment, filed 01 October 2024. The changes and remarks disclosed therein were considered.
Claim 1 has been canceled and claims 2-5 are newly added. Therefore, claims 2-5 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2010-205253 Japan 09/14/2010; JP2011-112791 Japan 05/19/2011).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 10/01/2024, 06/23/2025, 09/24/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 07/10/2024. These drawings are review and accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-5 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-6 of U.S Patent No. 12,040,042 B2 (‘042). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘042 claims.
US Patent No. 12,040,042 B2
US Patent Application No. 2025/0014615 A1
1. A semiconductor device comprising: a first transistor comprising: a first channel formation region comprising silicon; a first gate insulating film over the first channel formation region; and a first gate electrode over the first gate insulating film; a second transistor over the first transistor, the second transistor comprising: a second channel formation region comprising an oxide semiconductor film; a second gate insulating film over the second channel formation region; and a second gate electrode over the second gate insulating film; a first insulating film over the first gate electrode; a first conductive layer and a second conductive layer over the first insulating film; a second insulating film over the first conductive layer and the second conductive layer; a third insulating film over the second gate electrode; a fourth insulating film over the third insulating film; a third conductive layer in a first opening of the third insulating film and the fourth insulating film; a fourth conductive layer in a second opening of the third insulating film and the fourth insulating film; and a fifth conductive layer over the third conductive layer and the fourth conductive layer, the fifth conductive layer functioning as a wiring, wherein the first conductive layer comprises a region overlapping with the fifth conductive layer, wherein the second conductive layer comprises a region overlapping with the fourth conductive layer and the fifth conductive layer, wherein the third conductive layer comprises a region overlapping with the fifth conductive layer, and wherein the third conductive layer is electrically connected to the oxide semiconductor film.
2. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises indium.
3. A semiconductor device comprising: a first transistor comprising: a first channel formation region comprising silicon; a first gate insulating film over the first channel formation region; and a first gate electrode over the first gate insulating film; a second transistor over the first transistor, the second transistor comprising: a second channel formation region comprising an oxide semiconductor film; a second gate insulating film over the second channel formation region; and a second gate electrode over the second gate insulating film; a first insulating film over the first gate electrode; a first conductive layer and a second conductive layer over the first insulating film; a second insulating film over the first conductive layer and the second conductive layer; a third insulating film over the second gate electrode; a fourth insulating film over the third insulating film; a third conductive layer in a first opening of the third insulating film and the fourth insulating film; a fourth conductive layer in a second opening of the third insulating film and the fourth insulating film; and a fifth conductive layer over the third conductive layer and the fourth conductive layer, the fifth conductive layer functioning as a wiring.
4. The semiconductor device according to claim 3, wherein the oxide semiconductor film comprises indium.
5. A semiconductor device comprising: a first transistor comprising: a first channel formation region comprising silicon; a first gate insulating film over the first channel formation region; and a first gate electrode over the first gate insulating film; a second transistor over the first transistor, the second transistor comprising: a second channel formation region comprising an oxide semiconductor film; a second gate insulating film over the second channel formation region; a second gate electrode over the second gate insulating film; and a third gate electrode below the second channel formation region, the third gate electrode overlapping with the second gate electrode; a first insulating film over the first gate electrode; a first conductive layer and a second conductive layer over the first insulating film; a second insulating film over the first conductive layer and the second conductive layer; a third insulating film over the second gate electrode; a fourth insulating film over the third insulating film; a third conductive layer in an opening of the third insulating film; a fourth conductive layer over the third conductive layer, the fourth conductive layer functioning as a wiring, wherein the first conductive layer comprises a region overlapping with the fourth conductive layer, wherein the second conductive layer comprises a region overlapping with the fourth conductive layer, wherein the third conductive layer comprises a region overlapping with the fourth conductive layer, and wherein the third conductive layer is electrically connected to the oxide semiconductor film.
6. The semiconductor device according to claim 5, wherein the oxide semiconductor film comprises indium.
2. A semiconductor device comprising: a first transistor comprising: a first channel formation region comprising silicon; a first gate insulating film over the first channel formation region; and a first gate electrode over the first gate insulating film; and a second transistor over the first transistor, the second transistor comprising: a second channel formation region comprising an oxide semiconductor film; a second gate insulating film over the second channel formation region; a second gate electrode over the second gate insulating film; and a third gate electrode below the second channel formation region, the third gate electrode overlapping with the second gate electrode.
3. The semiconductor device according to claim 2, wherein the oxide semiconductor film comprises indium.
4. The semiconductor device according to claim 2, further comprising: a first insulating film over the first gate electrode; a first conductive layer and a second conductive layer over the first insulating film; a second insulating film over the first conductive layer and the second conductive layer; a third insulating film over the second gate electrode; a fourth insulating film over the third insulating film; a third conductive layer in an opening of the third insulating film; and a fourth conductive layer over the third conductive layer, the fourth conductive layer functioning as a wiring.
5. The semiconductor device according to claim 2, further comprising: a first insulating film over the first gate electrode; a first conductive layer and a second conductive layer over the first insulating film; a third conductive layer over the first conductive layer and the second conductive layer; and a fourth conductive layer over the third conductive layer, the fourth conductive layer functioning as a wiring, wherein the first conductive layer comprises a region overlapping with the fourth conductive layer, wherein the second conductive layer comprises a region overlapping with the fourth conductive layer, wherein the third conductive layer comprises a region overlapping with the fourth conductive layer, and wherein the third conductive layer is electrically connected to the oxide semiconductor film.
Allowable Subject Matter
Claims 2-5 are presently rejected under obviousness double patenting, but would be allowable provided that a terminal disclaimer is filed.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 01/23/2026