DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1, Modification A2, Modification B3 in the reply filed on 22 June 2026 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 11,532,744 B2 in view of Jiefeng Lin et al. (US 20200006467 A1).
Instant Application Claim (18/768,125)
US 11,532,744 B2 Claim
Claim 1. A semiconductor device, comprising: a first gate structure disposed over a first backside dielectric feature; a second gate structure disposed over a second backside dielectric feature; and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature, wherein the gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.
1. A semiconductor device, comprising: a first gate structure disposed over a first backside dielectric feature; a second gate structure disposed over a second backside dielectric feature; a gate cut feature extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature; and a liner disposed between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature.
Claim 1 of 11,532,744 (hereinafter patent ‘744) does not expressly disclose wherein the gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.
In the same field of endeavor, Jiefeng Lin et al. (US 20200006467 A1; herein Lin) teaches utilizing an air gap (Fig. 6; 290; ¶0034) in a gate cut feature (300; ¶0035) laterally between a first (200A; ¶0020) and second (200B) gate structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Lin in the claim 1 of the ‘744 patent in order improve the dielectric properties of the gate cut feature (Lin; ¶0034).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiefeng Lin et al. (US 20200006467 A1; hereinafter Lin).
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Regarding Claim 1, Lin discloses a semiconductor device (Fig. 6), comprising:
a first gate structure (200A; ¶0033) disposed over a first backside dielectric feature (120 on the left of 150A; ¶0024; hereinafter 120L);
a second gate structure (200B; ¶0033) disposed over a second backside dielectric feature (120 on the right of 150B; ¶0024; hereinafter 120R); and
a gate cut feature (feature comprising 300 and 120 in the middle between 150A and 150B; ¶0025; hereinafter 300M) extending continuously from laterally between the first gate structure (200A) and the second gate structure (200B) to laterally between the first backside dielectric feature (120L) and the second backside dielectric feature (120R),
wherein the gate cut feature (300M) includes an air gap (290; ¶0034) laterally between the first gate structure (200A) and the second gate structure (200B).
Claims 11, 12, 13, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yeong Han Gwon et al. (US 20210035976 A1; hereinafter Gwon).
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Regarding Claim 11, Gwon discloses a semiconductor device (Fig. 9), comprising:
a first backside dielectric feature (left 105 which is on the backside of the gate; ¶0037; hereinafter 105L);
a plurality of first nanostructures (215_1; ¶0030) vertically stacked above the first backside dielectric feature (215_1 are vertically stacked at a level above 105L);
a first epitaxial feature (250; ¶0044) abutting the first nanostructures (215_1);
a first gate structure (220_1; ¶0030) wrapping around each of the first nanostructures (215_1);
a second backside dielectric feature (right 105 which is on the backside of the gate; hereinafter 105R);
a plurality of second nanostructures (115_1) vertically stacked above the second backside dielectric feature (115_1 are vertically stacked at a level above 105R);
a second epitaxial feature (150; ¶0040) abutting the second nanostructures (115_1);
a second gate structure (120_1; ¶0030) wrapping around each of the second nanostructures (115_1); and
a dielectric feature (160; ¶0030) extending vertically and continuously from a first position level with bottom surfaces of the first and second backside dielectric features (as shown by the horizontal dotted line in Fig. 9) to a second position level with or above top surfaces of the first and second gate structures (160 extends above top surfaces of 220_1 / 120_1).
Regarding Claim 12, Gwon discloses the semiconductor device of claim 11, wherein the dielectric feature (160) is in physical contact with the first (220_1) and second (120_1) gate structures (wherein the gate structures comprise the sidewall spacers 240 and 140 respectively; ¶0053; and as shown in Fig. 9).
Regarding Claim 13, Gwon discloses the semiconductor device of claim 11, wherein the dielectric feature (160) includes a bottom portion (annotated Fig. 9; BP) laterally between the first (105L) and second (105R) backside dielectric features and a top portion (annotated Fig. 9; TP) laterally between the first (220_1) and second gate structures (120_1), wherein the bottom portion (BP) is wider than the top portion (TP) (as shown in annotated Fig. 9).
Regarding Claim 16, Gwon discloses the semiconductor device of claim 11, wherein a top portion of the dielectric feature (a top of 160) is above the top surfaces of the first and second gate structures (as shown in Fig. 9).
Claims 17-19 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Min Seek Jo et al. (US 20190305099 A1; hereinafter Jo).
Regarding Claim 17, Jo discloses a semiconductor device (Fig. 1, Fig. 9, and Fig. 10; ¶0013), comprising:
an isolation feature (105; ¶0029);
a first gate structure (630; ¶0041) disposed on a top surface of the isolation feature (105);
a second gate structure (330; ¶0032) disposed on the top surface of the isolation feature (105);
an etch stop layer (645/345; ¶0032, ¶0041; commensurate in scope with the gate capping pattern 257 as an “etch stop” of the instant application at [0028]) disposed on top surfaces of the first (630) and second (330) gate structures; and
a dielectric feature (180; ¶0046) disposed between the first (630) and second (330) gate structures, wherein in a cross-sectional view perpendicular to a lengthwise direction of the first and second gate structures, the dielectric feature (180) extends vertically through the isolation feature (105) (Fig. 9) and interfaces with the etch stop layer (645/345) (Fig. 9).
Regarding Claim 18, Jo discloses the semiconductor device of claim 17, wherein the dielectric feature (180) has a lower portion surrounded by the isolation feature (105) and an upper portion laterally between the first (630) and second (330) gate structures, wherein the lower portion is wider than the upper portion (the lower portion is wider in the Y direction than the upper portion is in the X direction, as seen in view of Fig. 1, Fig. 9, and Fig. 10).
Regarding Claim 19, Jo discloses the semiconductor device of claim 17, wherein the dielectric feature (180) includes an air gap (180g; ¶0083) laterally between the first and second gate structures (as shown in view of Fig. 1, Fig. 9, and Fig. 10 wherein 180g is located at a position laterally between the first and second gate structures).
Regarding Claim 21, Jo discloses the semiconductor device of claim 17, wherein a top surface of the dielectric feature (180) is above the top surfaces of the first and second gate structures (as shown in Fig. 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hui Zhang et al. (US 20200168509 A1; hereinafter Zang) in view of Lin.
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Regarding Claim 1, Zang discloses a semiconductor device (see Fig. 9 in view of oriented Zang Fig. 9), comprising:
a first gate structure (left 20; ¶0018; hereinafter 20L) disposed over a first backside dielectric feature (left 38; ¶0024, which is interpreted as a backside in view of oriented Fig. 9 because the claim does not specify what “backside” is relative to; MPEP2111.01 II; hereinafter 38L);
a second gate structure (right 20; hereinafter 20R) disposed over a second backside dielectric feature (right 38; hereinafter 38R); and
a gate cut feature (54; ¶0033) extending continuously from laterally between the first gate structure (20L) and the second gate structure (20R) to laterally between the first backside dielectric feature (38L) and the second backside dielectric feature (38R).
Zang does not expressly disclose wherein the gate cut feature (54) includes an air gap laterally between the first gate structure and the second gate structure.
In the same field of endeavor, Lin teaches utilizing an air gap (Fig. 6; 290; ¶0034) in a gate cut feature (300; ¶0035) laterally between a first (200A; ¶0020) and second (200B) gate structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Lin in the device of Zang in order improve the dielectric properties of the gate cut feature (Lin; ¶0034).
Regarding Claim 2, modified Zang teaches the semiconductor device of claim 1, further comprising:
a liner (46; shown in view of Fig. 5; ¶0037) disposed laterally between the gate cut feature (54) and the first backside dielectric feature (38L) and laterally between the gate cut feature (54) and the second backside dielectric feature (38R).
Regarding Claim 3, modified Zang teaches the semiconductor device of claim 2, wherein the gate cut feature (54) is in physical contact with the first gate structure (20L) and the second gate structure (20R).
Regarding Claim 4, modified Zang teaches the semiconductor device of claim 1, wherein the air gap (as modified by air gap 290 of Lin) extends continuously from laterally between the first gate structure (20L) and the second gate structure (20R) to laterally between the first backside dielectric feature (38L) and the second backside dielectric feature (38R) (as modified by Lin, wherein the air gap 290 extends essentially the entire height of the gate cut feature 300, which would result in satisfying the above limitations).
Regarding Claim 5, modified Zang teaches the semiconductor device of claim 1, wherein the air gap (as modified by Lin; 290) is a first air gap, and wherein the gate cut feature (54) includes a second air gap (Lin; ¶0034, wherein 290 may be one or more air gaps) laterally between the first backside dielectric feature (38L) and the second backside dielectric feature (38R) (wherein the one or more air gap(s) 290 are located at a position that is laterally between 38L/38R).
Regarding Claim 6, modified Zang teaches the semiconductor device of claim 1, further comprising: a gate spacer (22; ¶0018; which spaces the gate structure 20L and 20R from features 12 and 16) disposed on sidewalls of the first gate structure (20L) and the second gate structure (20R) (as shown in Oriented Zang Fig. 9), wherein the gate cut feature (54) is in physical contact with the gate spacer (22) (as shown in oriented Fig. 9 wherein the top of 54 is in physical contact with the gate spacer 112).
Regarding Claim 10, modified Zang discloses the semiconductor device of claim 1, wherein a top surface of the gate cut feature (top of 54) is above a top surface of the first gate structure (labeled TS1) and a top surface of the second gate structure (labeled TS2).
Claims 1, 7, 9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gwon in view of Lin.
Regarding Claim 1, Gwon discloses a semiconductor device (Fig. 9), comprising:
a first gate structure (220_1; ¶0030) disposed over a first backside dielectric feature (left 105; ¶0037; hereinafter 105L);
a second gate structure(120_1; ¶0030) disposed over a second backside dielectric feature (right 105; hereinafter 105R); and
a gate cut feature (160; ¶0030) extending continuously from laterally between the first gate structure (220_1) and the second gate structure (120_1) to laterally between the first backside dielectric feature (105L) and the second backside dielectric feature (105R).
Gwon does not expressly disclose wherein the gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.
In the same field of endeavor, Lin teaches utilizing an air gap (Fig. 6; 290; ¶0034) in a gate cut feature (300; ¶0035) laterally between top portions of a first (200A; ¶0020) and second (200B) gate structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Lin in the device of Gwon in order improve the dielectric properties of the gate cut feature (Lin; ¶0034).
Regarding Claim 7, modified Gwon teaches the semiconductor device of claim 1, further comprising:
a plurality of first nanostructures (215_1; ¶0030) vertically stacked above the first backside dielectric feature (215_1 are vertically stacked at a level above 105L), wherein the first gate structure (220_1) wraps around each of the first nanostructures (215_1);
a first epitaxial feature (250; ¶0044) abutting the first nanostructures (215_1);
a plurality of second nanostructures (115_1) vertically stacked above the second backside dielectric feature (115_1 are vertically stacked at a level above 105R), wherein the second gate structure (120_1) wraps around each of the second nanostructures (115_1); and
a second epitaxial feature (150; ¶0040) abutting the second nanostructures (115_1).
Regarding Claim 9, modified Gwon teaches the semiconductor device of claim 7, wherein bottom surfaces of the first (250) and second (150) epitaxial features are uneven (the rounded bottom surfaces of 250 and 150 are uneven {not flat}).
Regarding Claim 14, Gwon discloses the semiconductor device of claim 13. However, Gwon does not expressly disclose wherein the top portion of the dielectric feature includes an air gap.
In the same field of endeavor, Lin teaches utilizing an air gap (Fig. 6; 290; ¶0034) in a gate cut feature (300; ¶0035) laterally between top portions of a first (200A; ¶0020) and second (200B) gate structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the air gap of Lin in the device of Gwon in order improve the dielectric properties of the gate cut feature (Lin; ¶0034).
Allowable Subject Matter
Claims 8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 8, the prior art of record teaches or discloses the semiconductor device of claim 7 as shown above.
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the first backside dielectric feature has a first top surface directly under the first epitaxial feature and a second top surface directly under the first gate structure, and wherein the first top surface is above the second top surface.
Regarding Claim 15, the prior art of record teaches or discloses the semiconductor device of claim 11 as shown above.
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the dielectric feature includes a liner disposed on sidewalls of the first and second backside dielectric features, wherein the liner is directly under the first and second gate structures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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