DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/10/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-12 of U.S. Patent No. 12,062,721 in view of Tang (CN 109755290B).
Regarding claim 11, Pat '721 discloses, in claim 11 and 12, a semiconductor structure, comprising:
an active region comprising a first channel region, a second channel region, and a source/drain region disposed between the first channel region and the second channel region; a first plurality of nanostructures over the first channel region; a second plurality of nanostructures over the second channel region (all limitations are the same with the limitations recited in claim 11 of Pat '721);
a first plurality of inner spacer features interleaving the first plurality of nanostructures; a second plurality of inner spacer features interleaving the second plurality of nanostructures (all limitations are the same with the limitations recited in claim 12 of Pat '721);
a source/drain feature disposed between the first plurality of nanostructures and the second plurality of nanostructures (all limitations are the same with the limitations recited in claim 11 of Pat '721).
Pat '721 does not explicitly disclose an active region comprising a first channel region, a second channel region, and a source/drain region disposed between the first channel region and the second channel region along a direction; a germanium layer disposed between the source/drain feature and the source/drain region.
Tang teaches, in at least figure 15 and related text (translated text), the device comprising an active region (200, page 12) comprising a first channel region (region of 200 under 220 of left transistor, page 12, figure), a second channel region (region of 200 under 220 of right transistor, page 12, figure), and a source/drain region (region of 200 under 2310, page 12, figure) disposed between the first channel region (region of 200 under 220 of left transistor, page 12, figure) and the second channel region (region of 200 under 220 of right transistor, page 12, figure) along a direction (horizontal direction, figure); a germanium layer (272, page 11) disposed between the source/drain feature (2310, page 12) and the source/drain region (region of 200 under 2310, page 12, figure), for the purpose of providing the electrical isolation between the source/drain and the substrate, but also reducing the large capacitance between the bottom gate of the nano-wire transistor and the source/drain (page 2).
Pat '721 and Tang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '721 with the specified features of Tang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '721 to have the active region comprising a first channel region, a second channel region, and a source/drain region disposed between the first channel region and the second channel region along a direction; the germanium layer disposed between the source/drain feature and the source/drain region, as taught by Tang, for the purpose of providing the electrical isolation between the source/drain and the substrate, but also reducing the large capacitance between the bottom gate of the nano-wire transistor and the source/drain (page 2, Tang).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (CN 109755290B).
Regarding claim 11, Tang discloses, in at least figure 15 and related text, a semiconductor structure, comprising:
an active region (200, page 12) comprising a first channel region (region of 200 under 220 of left transistor, page 12, figure), a second channel region (region of 200 under 220 of right transistor, page 12, figure), and a source/drain region (region of 200 under 2310, page 12, figure) disposed between the first channel region (region of 200 under 220 of left transistor, page 12, figure) and the second channel region (region of 200 under 220 of right transistor, page 12, figure) along a direction (horizontal direction, figure);
a first plurality of nanostructures (220 of left transistor, page 12, figure) over the first channel region (region of 200 under 220 of left transistor, page 12, figure);
a second plurality of nanostructures (220 of right transistor, page 12, figure) over the second channel region (region of 200 under 220 of right transistor, page 12, figure);
a source/drain feature (2310, page 12) disposed between the first plurality of nanostructures (220 of left transistor, page 12, figure) and the second plurality of nanostructures (220 of right transistor, page 12, figure); and
a germanium layer (272, page 11) disposed between the source/drain feature (2310, page 12) and the source/drain region (region of 200 under 2310, page 12, figure).
Tang does not explicitly disclose a first plurality of inner spacer features interleaving the first plurality of nanostructures; a second plurality of inner spacer features interleaving the second plurality of nanostructures.
Tang teaches, in at least figure 25 and related text (translated text), the device comprising a first plurality of inner spacer features (373, page 14) interleaving the first plurality of nanostructures (320 of left transistor, page 13, figure); a second plurality of inner spacer features (373, page 14) interleaving the second plurality of nanostructures (320 of left transistor, page 13, figure), for the purpose of providing the electrical isolation between the source/drain and the substrate, but also reducing the large capacitance between the bottom gate of the nano-wire transistor and the source/drain (page 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Tang’s figure 15 to have the first plurality of inner spacer features interleaving the first plurality of nanostructures; the second plurality of inner spacer features interleaving the second plurality of nanostructures, as taught by Tang’s figure 25, for the purpose of providing the electrical isolation between the source/drain and the substrate, but also reducing the large capacitance between the bottom gate of the nano-wire transistor and the source/drain (page 2, Tang).
Allowable Subject Matter
Claims 1-10 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 that recite "a top surface of the bottom dielectric feature is higher than a top surface of the first APT region or a top surface of the second APT region" in combination with other elements of the base claims 1.
Claims 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 11 and 12 that recite "the bottom dielectric feature at least partially covers a sidewall of a bottommost one of the first plurality of inner spacer features and a sidewall of a bottommost one of the second plurality of inner spacer features" in combination with other elements of the base claims 11 and 12.
Claims 18-20 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 18 that recite "a bottom dielectric feature disposed over the substrate and between the first APT region and the second APT region along the direction, wherein the bottom dielectric feature comprises: a first blocking layer adjacent the first APT region; a second blocking layer adjacent the second APT region; and a semiconductor oxide feature sandwiched between the first blocking layer and the second blocking layer along the direction" in combination with other elements of the base claims 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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