Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 10th, 2024 was filed prior to the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claims 1-5, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20230335602 A1; hereinafter Hsu) in view of Zheng et al (US 20120302038 A1; hereinafter Zheng).
Regarding claim 1, Hsu teaches the following limitations:
A method for forming a flash memory device (Fig. 1-13; [0006]), comprising:
providing a substrate (Fig. 10: substrate 100; [0007]), wherein
the substrate has shallow trench isolation features formed therein (Fig. 10: bottom isolation structure 140; [0012]);
forming isolation features on the corresponding shallow trench isolation features (Fig. 10: isolation structure 200 with liner 130; [0037]), wherein
the isolation features have a first type of stress;
performing a surface treatment process on surface portions of the isolation features (Fig. 8: third implantation process P3, forms a doped portion 200A of the isolation structure 200 and liner 130 becomes doped liner 130a after implantation; [0035]) to convert the first type of stress of the surface portions of the isolation features into a second type of stress;
forming a tunneling dielectric layer on the substrate (Fig. 8: pad layer 110 is a higk-k dielectric material such as silicon oxide; [0010]); and
forming a floating gate layer on the tunneling dielectric layer (Fig. 10: floating gate forms of layers 410B and 500; [0053]), wherein
the floating gate layer is in contact with the surface portions of the isolation feature (Fig. 10: layer 500 in contact with doped portion 200A and doped liner 130A which is the surface of isolation structure 200).
However, Hsu also discloses in paragraphs 14 and 15, an initial implantation process P1 and P2 before the surface treatment process P3.
However, Zheng teaches the following limitations not disclosed by Hsu:
the isolation features have a first type of stress ([0039], “shallow trench isolation structure with the stress of its isolation oxide being tuned by an ion implantation… the stress thereof is changed from a tensile stress into a compressive stress”, the isolation structure is stated to start with an initial stress);
performing a surface treatment process on surface portions of the isolation features to convert the first type of stress of the surface portions of the isolation features into a second type of stress ([0039], “the stress thereof is changed from a tensile stress into a compressive stress”, the second type of stress is the compressive stress converted);
Hsu also discloses in paragraph 13, that the isolation structure 200 may be silicon oxide, and in paragraph 36 that the dopant for the ion implantation may be the same as the process P1 and P2 disclosed in paragraph 15, which includes argon.
Zheng also discloses in paragraphs 3, that the shallow trench isolation feature is formed of high quality silicon dioxide (same as silicon oxide), and in paragraph 36 that the dopant of the ion implantation may be selected from a group including argon.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention that the implantation processes of Hsu is analogous to the process of Zheng, and would be motivated to induce a first type of stress in the isolation features and convert it into a second type of stress to tune the device and prevent the stresses on the surrounding device during the manufacturing process.
Regarding claim 3, Hsu teaches the method for forming a flash memory device as claimed in claim 1, wherein the surface treatment process comprises an ion implantation process (Fig. 8: third implantation process P3 performed on the isolation structure 200).
Regarding claim 4, Hsu teaches the method for forming a flash memory device as claimed in claim 3, wherein the ion implantation process implants a dopant in the surface portions of the isolation features (Fig. 8: implantation process P3 implants a dopant into 200 and forms the doped portion 200A into the isolation 200 and doped liner 130A of liner 130; [0035] – [0036]).
Regarding claim 5, Hsu teaches the method for forming a flash memory device as claimed in claim 4, wherein the dopant comprises boron, carbon, silicon, germanium, nitrogen, phosphorus, arsenic, fluorine, argon or a combination thereof ([0015], P-type dopants such as boron (B), N-type dopants such as nitrogen (N), phosphorus (P), arsenic (As) or dopants such as argon (Ar) may be implanted).
Regarding claim 9, Hsu teaches the method for forming a flash memory device as claimed in claim 1, wherein each of the isolation features has a central portion covered by the surface portion (Fig. 8: portion 200B of the isolation structure 200 is in the center and doped portion is on the top surface of the isolation structure), and the central portion has the first type of stress after performing the surface treatment process.
However, Zheng teaches the first type of stress after performing the surface treatment process ([0039], the first type of stress before the change is a tensile stress, which the undoped portions of the isolation feature would still contain after the ion implantation process)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the isolation region of Hsu with the stresses of Zheng in order to tune the amount of stress necessary during manufacturing so as to not damage the structure of the device.
Regarding claim 11, Hsu teaches the method for forming a flash memory device as claimed in claim 1, further comprising:
performing a planarization process to remove a portion of the floating gate layer and the surface portions of top surfaces of the isolation features to form floating gates after forming the floating gate layer (Fig. 11: planarization process removes a portion of the second conductive layer 500, the doped portion 200A of the isolation structure 200, and the doped portion 130A of the liner 130, formed after the formation of conductive layer 500 which becomes part of the floating gate; [0044]);
selectively etching the isolation features (Fig. 12: 200B is selectively etched-back to be lower than the remaining portion 500B; [0048]);
forming a gate dielectric layer on the selectively etched isolation features and the floating gates (Fig. 13: interlayer dielectric 600 formed covering isolation features 200 and floating gate 500; [0051]); and
forming a control gate layer on the gate dielectric layer (Fig. 13: third conductive layer 700; [0052]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Zheng as applied to claim 1 above, and further in view of Courboin et al. (Courboin, D., Grouillet, A., & Andre, E. (2000). Surface roughness of ion implanted 〈100〉 silicon studied by atomic force microscopy. Surface Science, 342(1–3), L1111–L1115. https://doi.org/10.1016/0039-6028(95)00827-6; hereinafter Courboin).
Regarding claim 2, Hsu does not explicitly teach he method for forming a flash memory device as claimed in claim 1, wherein the surface portions of the isolation features have a first roughness before performing the surface treatment process, and wherein the surface portions of the isolation features have a second roughness after performing the surface treatment process, wherein the second roughness is greater than the first roughness.
However, Hsu does teach in paragraph 35 and 36, the surface treatment process being performed is an ion implantation process.
However, Courboin teaches on page 1 paragraph 1, that an ion implantation process induces a level of surface roughness including experimental results on pages 2-4 of the roughness measured by standard roughness parameters (Rmax, RMS).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date to combine the ion implantation process of Hsu with the ion implantation process of Courboin in order to induce a roughness greater than the initial roughness after the process is performed.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Zheng as applied to claim 1 above, and further in view of Tian et al. (CN 112397518 A; hereinafter Tian).
Regarding claim 6, Hsu does not teach the method for forming a flash memory device as claimed in claim 4, further comprising: performing an annealing process to diffuse the dopant in the surface portions of the isolation features into the floating gate layer after forming the floating gate layer
However, Tian teaches performing an annealing process to diffuse the dopant in the surface portions of the isolation features into the floating gate layer after forming the floating gate layer (Fig. 3b: after the ion implantation process to dope the isolation structures 101’ and 102’, an annealing step allows the doped ions from the shallow trench isolation structures to diffuse into the floating gate layer 120; [0067] – [0069]).
Tian also teaches further in paragraph 69, that the annealing can prevent rapid crystallization at the bottom of the floating ate layer and reduce the polysilicon grain size at the interface between the floating gate and tunnel oxide layer.
It would be obvious to one or ordinary skill in the art before the effective filing date to combine the process of Hsu with the annealing of Tian in order to more evenly distribute the dopant throughout the floating gate and prevent rapid crystallization.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Zheng as applied to claim 1 above, and further in view of Zhang et al. (US 20240194518 A1; hereinafter Zhang).
Regarding claim 7, Hsu and Zheng do not explicitly teach the method for forming a flash memory device as claimed in claim 1, wherein the first type of stress is compressive stress, and wherein the second type of stress is tensile stress or neutral stress.
However, Zhang discloses wherein the first type of stress is compressive stress, and wherein the second type of stress is tensile stress or neutral stress (Fig. 3-4: ion implantation process 145 onto isolation regions 130B and 130C can result in either tensile or compressive stresses by changing factors such as the type of dopant and temperature of annealing, dopants including Si, C, N, and F, [0024] – [0025])
However, applicant discloses in paragraph [0013], a list of viable dopants including carbon, silicon, nitrogen, and fluorine.
It would have been obvious to one of ordinary skill in the art before the effective filing date to perform the surface treatment process of Hsu with the dopants of Zhang in order to have a first type of stress be a compressive stress, and induce a tensile stress into the device through ion implantation in order to tune the internal stresses within the device during manufacturing.
Regarding claim 8, Hsu and Zheng do not explicitly teach the method for forming a flash memory device as claimed in claim 1, wherein the first type of stress and the second type of stress are compressive stress, and a first stress value of the first type of stress is greater than a second stress value of the second type of stress.
However, Zhang teaches wherein the first type of stress and the second type of stress are compressive stress, and a first stress value of the first type of stress is greater than a second stress value of the second type of stress (Fig. 3-4: ion implantation process 145 onto isolation regions 130B and 130C can result in either tensile or compressive stresses by changing factors such as the type of dopant and temperature, dopants including Si, C, N, and F, [0024] – [0025]).
However, applicant discloses in paragraph [0013], a list of viable dopants including carbon, silicon, nitrogen, and fluorine.
It would have been obvious to one of ordinary skill in the art before the effective filing date to perform the surface treatment process of Hsu with the dopants of Zhang in order to have a first type of stress be a compressive stress, and induce a tensile stress into the device through ion implantation in order to tune the internal stresses within the device during manufacturing.
Allowable Subject Matter
Claims 10 and 12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the claim would be allowable for the formed capping layer specifically being formed after the surface treatment process and then the removing the capping layer on the substrate and top surfaces of the isolation features.
Hsu discloses the state of the art in Fig. 1 and paragraph 8, that mask layer 120 is formed before the first surface treatment process, however, does not disclose forming a capping layer. While the mask layer 120 could be interpreted to be formed on the substrate and sides of the isolation features, as depicted in Fig. 2, it is not formed after the surface treatment process and it would be improper hindsight to attempt to justify changing the ordering of the surface treatment process with the formation of the capping layer.
Regarding claim 12, the claim would be allowable for the isolation features having side surfaces connected to the top surfaces, and after performing the planarization process, a roughness of the top surfaces of the isolation features is smaller than a roughness of the side surfaces.
Hsu discloses the state of the art, where the doped portions of the surface of the isolation features are all planarized at the same time, Fig. 11 and paragraph 44-47, teaches that the doped portion 200A of the isolation structure 200, and the doped portion 130A of the liner 130 are both removed in the planarization process. While the remaining liner 130B may still be considered a side surface of the isolation feature, that portion is not stated to have been doped by the implantation process due to it being covered by 410B. it is not explicitly taught that the remaining liner would have an induced rough surface due to the implantation process and that it would be rougher than the planarized top of the isolation features.
Claims 13-17 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the claim would be allowable for the central portion covered by the surface portion, wherein the central portion has a first type of stress, and the surface portion has a second type of stress.
Hsu teaches in Fig. 13 and paragraphs 44 – 47, that the doped portion 200A of the isolation structure 200, and the doped portion 130A of the liner 130 are both removed during the planarization, and the final device does not contain isolation features where explicitly the central portion and surface portions have a first type of stress and a second type of stress, because the portion with the second type of stress has been planarized.
Regarding claim 14, the claim would be allowable because it is dependent on claim 13.
Regarding claim 15, the claim would be allowable because it is dependent on claim 13.
Regarding claim 16, the claim would be allowable because it is dependent on claim 13.
Regarding claim 17, the claim would be allowable because it is dependent on claim 13.
Conclusion
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/BENJAMIN HOANG TRAN/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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