DETAILED ACTION
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/29/2026, 03/04/2026, 01/10/2025 were filed after the mailing date of the application. The submission is following the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 5, 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al., U.S. Patent No. 8,999,766.
Regarding claim 1, Su discloses a method for fabricating a die layer in a 3D IC structure, the method comprising (Figs. 1-5):
forming a vertical interconnect structure (VIS) in a VIS cell in the die layer (TSV 212 passes through substrate 320, exclusion zone 314 laterally surrounds TSV 212, Fig. 4),
forming a first device in or on the die layer (transistor 312 formed outside exclusion zone 314, see abstract, Fig. 3),
forming a non-sensitive circuit in the VIS cell (N+ region 316 forms diode 414, located within zone 314, unused die area of the VIS cell, Fig. 4), and
forming a first signal line to connect to the first device and to the non-sensitive circuit (M1 conductor, interconnects TSV 212, diode 414, and gate/source/drain of the transistor, Fig. 4), the first signal line electrically connecting the first device to the non-sensitive circuit (M1 conductor provides the conductive connection between transistor and diode, Fig. 4).
Regarding claim 3, Su discloses forming VIS in the VIS cell prior to forming the non-sensitive circuit in the VIS cell (forming TSV, then forming diffusion region including diode region 316 (Cols. 7-8).
Regarding claim 4, it is inherent that determining the location son a substrate for devices, VIS cells, circuits… is necessarily part of actually fabricating the structures at those particular locations.
Regarding claim 5, Su discloses wherein forming the VIS in the VIS cell includes forming a through-silicon via (TSV) (Figs. 3-4).
Regarding claim 8, Su discloses forming the non-sensitive circuit in the VIS cell includes forming the non-sensitive circuit in unused die area of the VIS cell (diode 414 is specifically placed in the otherwise unused exclusion zone 314, Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al., U.S. Patent No. 8,999,766, in view of Sproch et al., U.S. Pub. No. 2020/0270597.
Regarding claim 9, Su fails to disclose forming a sensitive circuit in unused die area of the VIS cell.
Sproch discloses forming a sensitive circuit (transistor 412, including gate 414 and S/D regions 416/418 positioned near TSV 410, Fig. 4) in unused die area of the VIS cell ([0005]-[0007], putting a transistor sufficiently close that the TSV effect exceeds the limit that previously defined that exclusion zone or keep-away zone).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Su to form a transistor in the otherwise unused die area associated with the TSV/VIS cell as taught by Sproch in order to increase utilization of die area and provide a denser IC while accounting for TSV-induced effects on transistor performance.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al., U.S. Patent No. 8,999,766, in view of Elsherbini et al., U.S. Pub. No. 2020/0091128.
Regarding claim 10, Su fails to disclose wherein the VIS is one of a through-glass via or through-dielectric via.
Elsherbini discloses interconnects through the dielectric material, including conductive vias and/or conductive pillars [0042].
It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Su by employing the through-dielectric via as taught by Elsherbini in order provide an interconnect through dielectric material and thereby improve power efficiency and improve power delivery.
Allowable Subject Matter
Claims 2, 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations having the method of claim 1, comprising: forming a second device in or on the die layer, forming a sensitive circuit in the VIS cell, and forming a second signal line to connect to the second device and to the sensitive circuit, the second signal line electrically connecting the second device to the sensitive circuit (Claim 2), the method of claim 5 wherein forming the TSV includes: forming a first mask layer over a substrate, patterning the first mask layer to include first openings wherein VISs will formed, forming a conductive material in the first opening, removing the first mask layer, forming a second mask layer over the substrate, patterning the second mask layer to include second openings where insulating material will be formed around the conductive material, forming the insulating material in the second openings around the conductive material and removing the second mask layer (claim 6).
Claims 11-20 are allowed. The following is an examiner’s statement of reason for allowance:
Claims 11-15: None of the references of record teaches or suggests the claimed having, among other limitations cited in claim 11, further comprising forming a second die layer over the first die layer, forming a second device in or on the second die layer, wherein the first device is a different type of device from a type of device of the second device to produce a heterogeneous 3D integrated circuit structure.
Claims 16-20: None of the references of record teaches or suggests the claimed having, among other limitations cited in claim 16, further comprising: forming an intermediate conductive layer over the first die layer, forming a second die layer aligned with the intermediate conductive layer and the first die layer, forming a second VIS in a second VIS cell in the second die layer, forming a second device in or on the second die layer, forming a second non-sensitive circuit in the second VIS cell and disposed adjacent the second device and attaching the second die layer to the intermediate conductive layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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