DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, Embodiment I, Fig. 2H, claims 1-15 and 17-19, in the reply filed on September 15, 2026 is acknowledged. Claims 16 and 20 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8, 13, 15 and 17-19 is/are rejected under 35 U.S.C. 102(a)(a) as being anticipated by Hagimoto et al. (Hagimoto) (JP 2013073988 A1).
In regards to claim 8, Hagimoto (Figs. 2-7 and associated text) discloses a device, comprising: a first semiconductor device (item 2); a second semiconductor device (item 7); an atomic layer deposition (ALD) bonding layer (item 12) joining the first semiconductor device (item 2) and the second semiconductor device (item 7); and one or more metal contacts (items 33 or 67) in at least a portion of one or more of the first semiconductor device (item 2) or the second semiconductor device (item 2).
In regards to claim 13, Hagimoto (Figs. 2-7 and associated text) discloses wherein the ALD bonding layer (item 12) is a single ALD bonding layer (item 12) joining the first semiconductor device (item 2) and the second semiconductor device (item 7).
In regards to claim 15, Hagimoto (Figs. 2-7 and associated text) discloses a device, comprising: a first semiconductor device (item 2); a second semiconductor device (item 7) comprising one or more metal contacts (items 33 or 67); and a single atomic layer deposition (ALD) bonding layer joining (item 12) the first semiconductor device (item 2) and the second semiconductor device (item 7).
In regards to claim 17, Hagimoto (Figs. 2-7 and associated text) discloses wherein the second semiconductor device comprises at least one of an intermetal dielectric (IMD) layer (items 69 plus 67) or an epitaxial layer.
In regards to claim 18, Hagimoto (Figs. 2-7 and associated text) discloses wherein the IMD layer (items 69 plus 67) comprises the one or more metal contacts (item 67).
In regards to claim 19, Hagimoto (Figs. 2-7 and associated text) discloses wherein the IMD layer (items 69 plus 67) and the one or more metal contacts (item 67) are in contact with the single ALD layer (item 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hagimoto et al. (Hagimoto) (JP 2013073988 A1).
In regards to claim 1, Hagimoto (Figs. 2-7 and associated text) discloses a device (Figs. 2, 7), comprising: a first semiconductor device (item 2); a second semiconductor device (item 7); and an atomic layer deposition (ALD) bonding layer (item 12) joining the first semiconductor device (item 2) and the second semiconductor device (item 7), wherein the ALD bonding layer (item 12) has a thickness in a range from approximately 20 Angstroms to approximately 400 Angstroms (2 nm, which is 20 Angstroms), but does not specifically disclose wherein the ALD bonding layer (item 12) includes a ratio of silicon hydroxide and silicon monoxide in a range from approximately five percent to approximately twenty percent. Examiner notes that bonding layer can be made of an oxide film or a nitride film, for example silicon oxide (SiO .sub.2 ), hafnia (HfO .sub.2 ) or silicon nitride (SiN).
However, the applicant has not established the critical nature of an ALD bonding layer having a thickness ranging from approximately 20 Angstroms to 400 Angstroms. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges.
It would have been obvious to modify the invention to include a ratio of silicon hydroxide and silicon monoxide in a range from approximately five percent to approximately twenty percent, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ratio of silicon hydroxide and silicon monoxide in a range from approximately five percent to approximately twenty percent, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 2, Hagimoto does not specifically disclose wherein a uniformity of the ALD bonding layer is in a range from approximately one percent to approximately two percent to enable direct bonding of the first semiconductor device and the second semiconductor device. Hagimoto (Figs. 2-7 and associated text) does disclose “Next, since the ALD method is a method with good film thickness uniformity by film formation in units of atomic layers, the flatness of the bonding surfaces 41 and 71 flattened by CMP is maintained, and the uniform insulating thin films 12a and 12b are maintained. Is formed on the first substrate 2 and the second substrate 7. Bonding is achieved by the flat bonding surfaces on which the insulating thin films 12a and 12b are formed, so that bonding with excellent adhesion is performed, and bonding of substrates with improved bonding strength becomes possible”.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a uniformity of the ALD bonding layer being in a range from approximately one percent to approximately two percent to enable direct bonding of the first semiconductor device and the second semiconductor device, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 3, Hagimoto (Figs. 2-7 and associated text) discloses wherein the ALD bonding layer (item 12) includes a dielectric material (silicon oxide (SiO .sub.2 ), hafnia (HfO .sub.2 ) or silicon nitride (SiN)).
In regards to claim 4, Hagimoto (Figs. 2-7 and associated text) discloses wherein the ALD bonding layer (item 12) includes one or more of: silicon, silicon nitride, silicon oxide, silicon dioxide, an organo-silicate glass, or a spin-on organic polymeric dielectric (silicon oxide (SiO .sub.2 ), hafnia (HfO .sub.2 ) or silicon nitride (SiN)).
In regards to claim 5, Hagimoto (Figs. 2-7 and associated text) discloses wherein the first semiconductor device (item 2) includes one of a first semiconductor wafer (items 2a, 20) or a first semiconductor die (items 2a plus 2b plus 2c), and the second semiconductor device (item 7) includes one of a second semiconductor wafer (items 7a, 50) or a second semiconductor die (items 7a plus 7b plus 7c).
In regards to claim 6, Hagimoto (Figs. 2-7 and associated text) does not specifically disclose wherein a ratio of a thickness of the first semiconductor device and a thickness of the second semiconductor device is in a range of approximately 5 percent to approximately 30 percent.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ratio of a thickness of the first semiconductor device and a thickness of the second semiconductor device being in a range of approximately 5 percent to approximately 30 percent, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 7, Hagimoto (Figs. 2-7 and associated text) does not specifically disclose wherein a bonding strength of the ALD bonding layer is greater than two Joules per square meter to enable direct bonding of the first semiconductor device and the second semiconductor device. Hagimoto (Figs. 2-7 and associated text) does disclose “Next, since the ALD method is a method with good film thickness uniformity by film formation in units of atomic layers, the flatness of the bonding surfaces 41 and 71 flattened by CMP is maintained, and the uniform insulating thin films 12a and 12b are maintained. Is formed on the first substrate 2 and the second substrate 7. Bonding is achieved by the flat bonding surfaces on which the insulating thin films 12a and 12b are formed, so that bonding with excellent adhesion is performed, and bonding of substrates with improved bonding strength becomes possible”.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a bonding strength of the ALD bonding layer being greater than two Joules per square meter, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 14, Hagimoto (Figs. 2-7 and associated text) does not specifically disclose wherein the ALD bonding layer (item 12) includes a ratio of silicon hydroxide and silicon monoxide in a range from approximately five percent to approximately twenty percent.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a ratio of silicon hydroxide and silicon monoxide in a range from approximately five percent to approximately twenty percent, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hagimoto et al. (Hagimoto) (JP 2013073988 A1) in view of Wang et al. (Wang) (CN 109891582 A).
In regards to claim 9, Hagimoto does not specifically disclose wherein the one or more metal contacts comprise a first metal contact, wherein, in a cross-section of the device, the first metal contact is in at least a portion of the first semiconductor device and in an entirety of the ALD bonding layer.
In regards to claim 9, Wang (Figs. 2A, 2B, 3, 6, 9 and associated text and items) discloses wherein the one or more metal contacts (items 212 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218 plus 212) comprise a first metal contact (items 232-1 plus 232-2 plus 218), wherein, in a cross-section of the device (item 200), the first metal contact (items 232-1 plus 232-2 plus 218) extends through at least a portion of the first semiconductor device (items 204 or 202) and through an entirety of the ALD bonding layer (items 216 plus 230).
In regards to claim 10, Wang (Figs. 2A, 2B, 3, 6, 9 and associated text and items) discloses wherein the one or more metal contacts (items 212 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218 plus 212) comprise a second metal contact (items 226 or 212), wherein, in a cross-section of the device, the first metal contact (items 212 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218 plus 212) further extends through at least a portion of the second semiconductor device (items 204 or 202).
In regards to claim 11, Wang (Figs. 2A, 2B, 3, 6, 9 and associated text and items) discloses wherein, in a cross-section of the device, the second metal contact(items 226 or 212) resides over, and is in contact with, the first metal contact (items 212 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218 plus 212).
In regards to claim 12, Wang (Figs. 2A, 2B, 3, 6, 9 and associated text and items) discloses a passivation layer (shown but not labeled, layer above or below item 237, Figs. 2A, 2B) over the second semiconductor device (item 204), wherein, in the cross-section of the device, the first metal contact (items 212 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218, or 226 plus 232-1 plus 232-2 plus 218 plus 212) extends through the passivation layer (shown but not labeled, layer above or below item 237, Figs. 2A, 2B).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Wang for the purpose of an electrical connection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang et al. (US 2015/0054161 A1) could have been as evidence in regards to the passivation layer of claim 12. Examiner suggests that the Applicant review all prior art from prosecution history of the parent application before responding in order promote compact prosecution.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 30, 2026
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