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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 3, 15, 20 of U.S. Patent No. 12074166, in view of Li (USPGPUB DOCUMENT: 2020/0279779, hereinafter Li).
Re claim 1 claim(s) 1, 3 of U.S. Patent No. 12074166 teaches device comprising: a semiconductor substrate; isolation regions extending into the semiconductor substrate; a semiconductor fin between the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions; a gate stack on a top surface and sidewalls of the semiconductor fin; and an epitaxy source/drain region on a side of the semiconductor fin, wherein the epitaxy source/drain region extends to a level lower than top surfaces of the isolation regions, and wherein the epitaxy source/drain region comprises: a first semiconductor layer having a first dopant concentration; and an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor has an upper portion higher than the top surface of the semiconductor fin, and a lower portion lower than the top surface of the semiconductor fin; a first fin spacer and a second fin spacer on opposing sides of the semiconductor fin, wherein the first semiconductor layer has an additional top surface, and a lowest point of the additional top surface is level with or lower than top ends of the first fin spacer and the second fin spacer.
Claim(s) 1, 3 of U.S. Patent No. 12074166 do not disclose a first semiconductor strip and a second semiconductor strips between the isolation regions, a first semiconductor fin and a second semiconductor fin directly over the first semiconductor strip and the second semiconductor strip, respectively; wherein the epitaxy source/drain region comprises: a first semiconductor layer comprising a first portion and a second portion over and contacting the first semiconductor strip and the second semiconductor strip, respectively, wherein the second semiconductor layer comprises a middle part separating the first portion from the second portion.
Li discloses a first semiconductor strip(left/right portion of 110 between 125’s) and a second semiconductor strips(left/right of 110 between 125’s of Li) between the isolation regions(left/right 125), respectively, wherein the second semiconductor layer(120-1/120-2/115/180) comprises a middle part separating the first portion from the second portion.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of US Patent No. 12074166 in order to reduce the gate-to-source/drain parasitic capacitance, [0004, Li]. In doing so, a first semiconductor fin and a second semiconductor fin [US Patent No. 12074166] directly over the first semiconductor strip(left/right of 110 between 125’s of Li) and the second semiconductor strip(left/right of 110 between 125’s of Li), respectively; wherein the epitaxy source/drain region [US Patent No. 12074166] comprises: a first semiconductor layer comprising a first portion and a second portion over and contacting the first semiconductor strip and the second semiconductor strip,
Re claim 2 US Patent No. 12074166 and Li disclose the device of claim 1 further comprising a void underlying the middle part of the second semiconductor layer(120-1/120-2/115/180 of Li).
Re claim 3 US Patent No. 12074166 and Li disclose the device of claim 2, wherein the first semiconductor layer(120-1/120-2/115/180 of Li) is exposed to the void.
Re claim 4 US Patent No. 12074166 and Li disclose the device of claim 2, wherein the second semiconductor layer(120-1/120-2/115/180 of Li) is exposed to the void.
Re claim 5 US Patent No. 12074166 and Li disclose the device of claim 1 further comprising a silicide region over and contacting the second semiconductor layer(120-1/120-2/115/180 of Li).
Re claim 6 US Patent No. 12074166 and Li disclose the device of claim 5 further comprising: a third semiconductor layer(120-1/120-2/115/180 of Li) over the second semiconductor layer(120-1/120-2/115/180 of Li); and a contact plug over and contacting the silicide region to form a combined conductive region, wherein the combined conductive region penetrates through the third semiconductor layer(120-1/120-2/115/180 of Li).
Re claim 7 US Patent No. 12074166 and Li disclose the device of claim 6, wherein the third semiconductor layer(120-1/120-2/115/180 of Li) comprises a convex top surface, and wherein the combined conductive region penetrates through the convex top surface.
Re claim 8 US Patent No. 12074166 and Li disclose the device of claim 7, wherein the second semiconductor layer(120-1/120-2/115/180 of Li) comprises a concave top surface directly underly the convex top surface.
Re claim 9 US Patent No. 12074166 and Li disclose the device of claim 6, wherein the second semiconductor layer(120-1/120-2/115/180 of Li) is of p-type.
Re claim 10 US Patent No. 12074166 and Li disclose the device of claim 1, wherein the first semiconductor layer(120-1/120-2/115/180 of Li) has a first dopant concentration, and the second semiconductor layer(120-1/120-2/115/180 of Li) has a second dopant concentration higher than the first dopant concentration, and wherein the second semiconductor layer(120-1/120-2/115/180 of Li) has an upper portion higher than the top surface of the first semiconductor fin, and a lower portion lower than the top surface of the first semiconductor fin.
Re claim 11 US Patent No. 12074166 and Li disclose the device of claim 1, wherein the epitaxy source/drain region has a cone shape in a cross-section of the device[U.S. Patent No. 12074166].
Re claim 12 claim(s) 15, 20 of U.S. Patent No. 12074166 teaches a device comprising: a semiconductor substrate; isolation regions extending into the semiconductor substrate; a semiconductor fin between the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions; a gate stack on a top surface and sidewalls of the semiconductor fin; a gate spacer contacting the gate stack; and an epitaxy source/drain region on a side of the semiconductor fin, wherein the epitaxy source/drain region extends to a level lower than top surfaces of the isolation regions, and wherein the epitaxy source/drain region comprises: a first semiconductor layer having a first dopant concentration; and an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor comprises: an upper portion higher than the top surface of the semiconductor fin to contact a sidewall of the gate spacer; and a lower portion lower than the top surface of the semiconductor fin; wherein the epitaxy source/drain region has a wavy top surface, and the epitaxy source/drain region is of n-type, and the device further comprises: additional isolation regions extending into the semiconductor substrate; an additional semiconductor fin protruding higher than top surfaces of the additional isolation regions; an additional gate stack on a top surface and sidewalls of the additional semiconductor fin; and an additional epitaxy source/drain region on a side of the additional semiconductor fin, wherein the additional epitaxy source/drain region extends to an additional level lower than top surfaces of the additional isolation regions, and a top portion of the additional epitaxy source/drain region has a cone shape, and wherein the additional epitaxy source/drain region is of p-type.
Claim(s) 15, 20 of U.S. Patent No. 12074166 do not disclose wherein in a cross-section of the first gate stack, wherein the cross-section is perpendicular to a vertical plane that is parallel to a lengthwise direction of the first gate stack, a second semiconductor layer over and contacting the first semiconductor layer, wherein the second semiconductor layer has a concave top surface; and a third semiconductor layer over and contacting the second semiconductor layer, wherein the third semiconductor layer has a convex top surface directly over the concave top surface.
Li discloses wherein in a cross-section of the first gate stack(142/144/150), wherein the cross-section is perpendicular to a vertical plane that is parallel to a lengthwise direction of the first gate stack, a second semiconductor layer(120-1/120-2/115/180) over and contacting the first semiconductor layer(120-1/120-2/115/180), wherein the second semiconductor layer(120-1/120-2/115/180) has a concave top surface; and a third semiconductor layer(120-1/120-2/115/180) over and contacting the second semiconductor layer, wherein the third semiconductor layer has a convex top surface directly over the concave top surface.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of US Patent No. 12074166 in order to reduce the gate-to-source/drain parasitic capacitance, [0004, Li].
Re claim 13 US Patent No. 12074166 and Li disclose the device of claim 12, wherein the first semiconductor layer(120-1/120-2/115/180 of Li) has a first germanium atomic percentage, the second semiconductor layer(120-1/120-2/115/180 of Li) has a second germanium atomic percentage higher than the first germanium atomic percentage, and the third semiconductor layer(120-1/120-2/115/180 of Li) has a third germanium atomic percentage higher than the second germanium atomic percentage.
Re claim 14 US Patent No. 12074166 and Li disclose the device of claim 12 further comprising: a second semiconductor fin; a second gate stack on the second semiconductor fin[U.S. Patent No. 12074166]; and a second epitaxy semiconductor region aside of the second semiconductor fin, wherein the second epitaxy semiconductor region comprises an embedded stressor, and the embedded stressor comprises: a V-shaped bottom surface, wherein a top end of the V-shaped bottom surface is at a level lower than a top surface of the second semiconductor fin[U.S. Patent No. 12074166]; and a V-shaped top surface, wherein a first portion of the V-shaped top surface is higher than the top surface of the second semiconductor fin, and a second portion of the V-shaped top surface is lower than the top surface of the second semiconductor fin[U.S. Patent No. 12074166].
Re claim 15 US Patent No. 12074166 and Li disclose the device of claim 14 further comprising an additional semiconductor layer(120-1/120-2/115/180 of Li) underlying the embedded stressor, wherein the additional semiconductor layer(120-1/120-2/115/180 of Li) comprises a facet on a (111) surface plane of the additional semiconductor layer(120-1/120-2/115/180 of Li).
Re claim 16 US Patent No. 12074166 and Li disclose the device of claim 15, wherein the facet on the (111) surface plane extends to join a top corner of the second semiconductor fin.
Re claim 17 US Patent No. 12074166 and Li disclose the device of claim 12 further comprising a silicide region over and contacting the second semiconductor layer(120-1/120-2/115/180 of Li), wherein the silicide region is lower than a top surface of the third semiconductor layer(120-1/120-2/115/180 of Li).
Re claim 18 claim(s) 15, 20 of U.S. Patent No. 12074166 teaches teaches a device comprising: a semiconductor substrate; isolation regions extending into the semiconductor substrate; a semiconductor fin between the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions; a gate stack on a top surface and sidewalls of the semiconductor fin; a gate spacer contacting the gate stack; and an epitaxy source/drain region on a side of the semiconductor fin, wherein the epitaxy source/drain region extends to a level lower than top surfaces of the isolation regions, and wherein the epitaxy source/drain region comprises: a first semiconductor layer having a first dopant concentration; and an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor comprises: an upper portion higher than the top surface of the semiconductor fin to contact a sidewall of the gate spacer; and a lower portion lower than the top surface of the semiconductor fin; wherein the epitaxy source/drain region has a wavy top surface, and the epitaxy source/drain region is of n-type, and the device further comprises: additional isolation regions extending into the semiconductor substrate; an additional semiconductor fin protruding higher than top surfaces of the additional isolation regions; an additional gate stack on a top surface and sidewalls of the additional semiconductor fin; and an additional epitaxy source/drain region on a side of the additional semiconductor fin, wherein the additional epitaxy source/drain region extends to an additional level lower than top surfaces of the additional isolation regions, and a top portion of the additional epitaxy source/drain region has a cone shape, and wherein the additional epitaxy source/drain region is of p-type.
Claim(s) 15, 20 of U.S. Patent No. 12074166 do not teaches wherein the epitaxy source/drain region comprises: a first semiconductor layer having a first concave top surface; and a second semiconductor layer over and contacting the first semiconductor layer, wherein the second semiconductor layer has a second concave top surface; and a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer has a convex top surface.
Li discloses wherein the epitaxy source/drain region comprises: a first semiconductor layer(120-1/120-2/115/180) having a first concave top surface; and a second semiconductor layer(120-1/120-2/115/180) over and contacting the first semiconductor layer, wherein the second semiconductor layer has a second concave top surface; and a third semiconductor layer(120-1/120-2/115/180) over the second semiconductor layer, wherein the third semiconductor layer has a convex top surface.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Li to the teachings of US Patent No. 12074166 in order to reduce the gate-to-source/drain parasitic capacitance, [0004, Li].
Re claim 19 US Patent No. 12074166 and Li disclose the device of claim 18, wherein the epitaxy source/drain region(region of 120-1/120-2/115/180 of Li) has a cone shape in a cross-section of the device.
Re claim 20 US Patent No. 12074166 and Li disclose the device of claim 18, wherein the first concave top surface(please see region of 120-1/120-2/115/180 of Li) comprises a first part and a second part close to and separated from each other.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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