DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows:
Claims 1-12 are pending.
Claims 1 and 7 are amended.
An action on the merits for claims 1-12 follows.
Priority Claims
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Specification
Applicant’s amendment of the title is acknowledged. Examiner hereby withdraws the objection to the title.
Response to Arguments
Applicants’ arguments filed 09/16/2026 have been fully considered but are not found to be persuasive in light of applicants’ claim amendments. Regarding applicant’s argument on pg. 12 that the encapsulation layer is a single structure integrally formed of the insulating material containing the magnetic material and directly contacts and encapsulates the plurality of conductive pillars, this is not found persuasive because these limitations have not been added to the claims. The encapsulation layer being integrally formed and directly contacting the plurality of conductive pillars are currently unclaimed limitations and have no bearing on the prior art rejection. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1933). Examiner recommends that Applicant amend these limitations into the claims if they are the intended distinguishing features over the cited prior art.
In response to applicant’s argument on pg. 15 that the magnetic layer of Fig. 2 of Liu is not formed integrally as a single structure and that the magnetic layer of Fig. 4 of Liu does not contact the interconnects, these are not found persuasive as the claimed limitations do not require either the magnetic layer to be formed integrally or for the magnetic layer to “directly” contact the interconnects.
Applicant’s argument on pg. 16 that Liu does not disclose that the inductor includes a magnetic layer or encapsulation layer containing a magnetic material is unpersuasive. Claims 1 and 7 of the present application indicate that the conductor structure and encapsulation layer constitute an inductor module and Liu clearly discloses that the conductor structure and encapsulation layer form an inductor module by way of the conductor structure via the plurality of interconnects of Liu. Applicant further elaborates that an inductor may have a hollow structure and that Liu does not specify a magnetic material/encapsulation layer within the interconnects and that this distinguishes the present application from Liu. This is considered non-pertinent as neither is drawn to a hollow structure inductor module, Liu clearly discloses being surrounded by a magnetic material such that it can be inferred it is part of the inductor module, and furthermore that the conductor structure and encapsulation layer make up an inductor module by way of Liu’s conductor structure (plurality of interconnects).
Applicant’s argument that the structure of Yu has differences from the claimed structure is unpersuasive. Yu teaches the specified limitations in the 103 section of the prior art rejection, teaches a motivation to combine with Liu and therefore does not need to teach each and every claimed limitation that is already taught by Liu.
In summary, neither applicants’ arguments nor amendments overcome the prior art rejection of record. An updated rejection in light of the new claim amendments follows for claims 1-12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 20240006308 A1), hereinafter Liu.
Regarding Claim 1, Liu teaches a semiconductor device ("integrated passive device," (201); Fig. 2 (profile cross-sectional view), Paragraph [0032]), comprising:
a carrier structure ("die substrate," (200); Fig. 4, Paragraph [0032]);
a first wiring layer (layer including "dielectric layer," (220) and "interconnect," (221); Paragraph [0032]) formed on the carrier structure (200);
a bottom routing layer (layer including "interconnect," (222); Paragraph [0032]) formed on the carrier structure (200);
a plurality of conductive pillars ("interconnect," (232); Paragraph [0032]) disposed on the carrier structure (200) and electrically connected to the first wiring layer (220, 221) and the bottom routing layer (222);
an encapsulation layer ("magnetic layer," (240); Paragraph [0032]) formed on the first wiring layer (220, 221) and the bottom routing layer (222) and touching and covering a surrounding surface of each of the plurality of conductive pillars (232), wherein the encapsulation layer (240) includes a magnetic material ("may include various magnetic materials;" Paragraph [0036]);
a top routing layer (layer including "interconnect," (251); Paragraph [0032]) formed on the encapsulation layer (240); and
a second wiring layer (layer including "dielectric layer," (260) and "interconnect," (261); Paragraph [0032]) formed on the encapsulation layer (240),
wherein the plurality of conductive pillars (232) are electrically connected to the top routing layer (251) and the second wiring layer (260, 261), wherein the bottom routing layer (222), the plurality of conductive pillars (232), and the top routing layer (251) constitute a conductor structure ("interconnects," (202); Paragraph [0034]), and the conductor structure (202) and the encapsulation layer (240) confined by the conductor structure (202) constitute an inductor module ("may be configured to operate as an inductor;" Paragraph [0034]).
(Note: Figs. 3, 8 also shows a plan view of a semiconductor device that is substantially similar to Fig. 2.)
(With regards to the claim amendments of the encapsulation layer touching and covering a surrounding surface of each of the plurality of conductive pillars, it should be noted that the claim does not require the encapsulation layer to be “directly touching,” as in having no intervening elements between, and that “covering a surrounding surface” is being applied to be covering a surface of the conductive pillars laterally).
Regarding Claim 3, Liu teaches the semiconductor device of claim 1, wherein each of the first wiring layer (220, 221), the bottom routing layer (222), the top routing layer (251), and the second wiring layer (260, 261) is a redistribution layer ("plurality of interconnects 202 may include [221, 222, 251, 261];" Paragraph [0032]; "may include a plurality of redistribution interconnects;" Paragraph [0035]).
Regarding Claim 4, Liu teaches the semiconductor device of claim 1, wherein the first wiring layer (220, 221) includes a first insulator ("dielectric layer," (220); Paragraph [0032]) and a plurality of first conductive wirings ("interconnect," (221); Paragraph [0032]) bonded to the first insulator (220), the bottom routing layer (222) includes a plurality of bottom wirings (plurality of (222); Fig. 2, Paragraph [0032]), the top routing layer (251) includes a plurality of top wirings (plurality of (251); Fig. 2, Paragraph [0032]), and the second wiring layer (260, 261) includes a second insulator ("dielectric layer," (260); Paragraph [0032]) and a plurality of second conductive wirings (interconnect," (261); Paragraph [0032]) bonded to the second insulator (260).
Regarding Claim 5, Liu teaches the semiconductor device of claim 4, wherein each of the conducive pillars (232) has a first end portion (1st End; Annotated Fig. 2) and a second end portion (2nd End; Annotated Fig. 2) opposing the first end portion (1st End), the first end portions (1st End) are optionally electrically connected to the plurality of bottom wirings (222) and/or the plurality of first conductive wirings (221), and the second end portions (2nd End) are optionally electrically connected to the plurality of top wirings (251) and/or the plurality of second conductive wirings (261).
(Note: herein (and in reference to claim 11) the term “optionally is interpreted to mean as referring to the option of selecting either or both options delineated by the “and/or” and that the end portion must be electrically connected to at least one of them.
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Regarding Claim 6, Liu teaches the semiconductor device of claim 1, wherein the encapsulation layer (240) has a first surface (1st Surface; Annotated Fig. 2) and a second surface (2nd Surface; Annotated Fig. 2) opposing the first surface (1st Surface), the encapsulation layer (240) is disposed on the first wiring layer (220, 221) and the bottom routing layer (222) via the first surface (1st Surface) thereof, and the plurality of conductive pillars (232) are exposed out from the second surface (2nd Surface) of the encapsulation layer (240).
Regarding Claim 7, Liu teaches a method of manufacturing a semiconductor device (“integrated passive device,” (201); Figs. 2, 12A-12E, Paragraph [0079]; “the sequence may be used to provide or fabricate […] the integrated passive device 201” as in Fig. 2), the method comprising:
providing a carrier structure (“die substrate,” (200); Fig. 12A, Paragraph [0081]);
forming a first wiring layer (layer including "dielectric layer," (220) and "interconnect," (221); Paragraphs [0082, 0083]),
a bottom routing layer (layer including "interconnect," (222); Fig. 12B, Paragraph [0084]), and
a plurality of conductive pillars ("interconnect," (232); Paragraph [0084]) on the carrier structure (200), and electrically connecting the plurality of conductive pillars (232) to the first wiring layer (layer including 220, 221) and the bottom routing layer (layer including 222);
forming an encapsulation layer ("magnetic layer," (240); Fig. 12C, Paragraph [0086]) touching and covering a surrounding surface of each of the plurality of conductive pillars (232) on the first wiring layer (220, 221) and the bottom routing layer (222), wherein the encapsulation layer (240) includes a magnetic material (“magnetic layer;” Paragraph [0086]); and
forming a top routing layer (layer including "interconnect," (251); Fig. 12D, Paragraph [0089]) and
a second wiring layer (layer including "dielectric layer," (260) and "interconnect," (261); Figs. 12D-12E, Paragraphs [0089, 0090]) on the encapsulation layer (240), and
electrically connecting the plurality of conductive pillars (232) to the top routing layer (251) and the second wiring layer (260, 261), wherein the bottom routing layer (222), the plurality of conductive pillars (232), and the top routing layer (251) constitute a conductor structure ("interconnects," (202); Paragraph [0034]), and the conductor structure (202) and the encapsulation layer (240) confined by the conductor structure (202) constitute an inductor module ("may be configured to operate as an inductor;" Paragraph [0034]; “the sequence may be used to provide or fabricate […] the integrated passive device 201;” Paragraph [0079]).
(Note: Figs. 2, 3, 8 also shows views of a semiconductor device that is substantially similar to the method process of Figs. 12A-12E)
(With regards to the claim amendments of the encapsulation layer touching and covering a surrounding surface of each of the plurality of conductive pillars, it should be noted that the claim does not require the encapsulation layer to be “directly touching,” as in having no intervening elements between, and that “covering a surrounding surface” is being applied to be covering a surface of the conductive pillars laterally).
Regarding Claim 9, Liu teaches the method of claim 7, wherein each of the first wiring layer (220, 221), the bottom routing layer (222), the top routing layer (251), and the second wiring layer (260, 261) is a redistribution layer ("plurality of interconnects 202 may include [221, 222, 251, 261];" Paragraph [0032]; "may include a plurality of redistribution interconnects;" Paragraph [0035]).
Regarding Claim 10, Liu teaches the method of claim 7, wherein the first wiring layer (220, 221) includes a first insulator ("dielectric layer," (220); Paragraph [0032]) and a plurality of first conductive wirings ("interconnect," (221); Paragraph [0032]) bonded to the first insulator (220), the bottom routing layer (222) includes a plurality of bottom wirings (plurality of (222); Fig. 2, Paragraph [0032]), the top routing layer (251) includes a plurality of top wirings (plurality of (251); Fig. 2, Paragraph [0032]), and the second wiring layer (260, 261) includes a second insulator ("dielectric layer," (260); Paragraph [0032]) and a plurality of second conductive wirings (interconnect," (261); Paragraph [0032]) bonded to the second insulator (260).
Regarding Claim 11, Liu teaches the method of claim 10, wherein each of the conducive pillars (232) has a first end portion (1st End; Annotated Fig. 2) and a second end portion (2nd End; Annotated Fig. 2) opposing the first end portion (1st End), the first end portions (1st End) are optionally electrically connected to the plurality of bottom wirings (222) and/or the plurality of first conductive wirings (221), and the second end portions (2nd End) are optionally electrically connected to the plurality of top wirings (251) and/or the plurality of second conductive wirings (261). (Note: Annotated Fig. 2 shows a device made by the same method as in Figs. 12A-12E; Paragraph [0079])
Regarding Claim 12, Liu teaches the method of claim 7, wherein the encapsulation layer (240) has a first surface (1st Surface; Annotated Fig. 2) and a second surface (2nd Surface; Annotated Fig. 2) opposing the first surface (1st Surface), the encapsulation layer (240) is disposed on the first wiring layer (220, 221) and the bottom routing layer (222) via the first surface (1st Surface) thereof, and the plurality of conductive pillars (232) are exposed out from the second surface (2nd Surface) of the encapsulation layer (240). (Note: Annotated Fig. 2 shows a device made by the same method as in Figs. 12A-12E; Paragraph [0079])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Yu et al. (US 20190035877 A1), hereinafter Yu
Regarding Claim 2, Liu teaches the semiconductor device of claim 1.
Liu does not explicitly teach wherein the first wiring layer is electrically connected to the carrier structure.
Yu teaches at least a semiconductor device ("wafer package structure," (20); Figs. 2A-2E, Paragraph [0028]) wherein the first wiring layer ("redistribution layer," (210); Fig. 2A, Paragraph [0023]) is electrically connected to the carrier structure ("carrier," (202); Fig. 2A, Paragraph [0022]; they are electrically connected by the "metallization pattern," (212); Fig. 2A, Paragraph [0022]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu with the device of Liu such that the first wiring layer is electrically connected to the carrier structure. Since the first wiring layer is part of an inductor module (or made of an inductor pattern Paragraph [0022]), being electrically connected to the carrier has the added benefit of allowing the inductor to be electrically connected to the rest of the semiconductor chip/package on the carrier. This allows the inductor module to function as part of a larger device (Paragraphs [0022, 0034, 0035]).
Regarding Claim 8, Liu teaches the method of claim 7.
Liu does not explicitly teach wherein the first wiring layer is electrically connected to the carrier structure.
Yu teaches at least a method for forming a semiconductor device ("wafer package structure," (20); Figs. 2A-2E, Paragraph [0028]) wherein the first wiring layer ("redistribution layer," (210); Fig. 2A, Paragraph [0023]) is electrically connected to the carrier structure ("carrier," (202); Fig. 2A, Paragraph [0022]; they are electrically connected by the "metallization pattern," (212); Fig. 2A, Paragraph [0022]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Yu with the device of Liu such that the first wiring layer is electrically connected to the carrier structure. Since the first wiring layer is part of an inductor module (or made of an inductor pattern Paragraph [0022]), being electrically connected to the carrier has the added benefit of allowing the inductor to be electrically connected to the rest of the semiconductor chip/package on the carrier. This allows the inductor module to function as part of a larger device (Paragraphs [0022, 0034, 0035]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOLAN G STUESSY whose telephone number is (571)645-5843. The examiner can normally be reached 7:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOLAN G STUESSY/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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