DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-14, in the reply filed on 8/18/2026 is acknowledged.
Claims 15-20 have been canceled. Claims 21-26 have been added.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-4, 6, 8-9, 21-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12 and 17 of U.S. Patent No. 11527533 B2, respectively. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, claim 1 of US 11527533 B2 teaches a semiconductor structure comprising:
a fin-shaped structure (US 11527533 B2, claim 1, column 9 line 63);
a gate structure (US 11527533 B2, claim 1, column 10 lines 10-16) disposed over a region of the fin-shaped structure and having a sidewall including a lower portion and an upper portion above the lower portion (column 10 lines 13-16);
a first dielectric sidewall structure disposed along the lower portion of the sidewall (US 11527533 B2, claim 1, column 10 lines 13-14);
a second dielectric sidewall structure disposed along the upper portion of the sidewall and disposed on the first dielectric sidewall structure (US 11527533 B2, claim 1, column 10 lines 15-16); and
a source/drain feature disposed over a source/drain region of the fin-shaped structure and adjacent to the gate structure, wherein the source/drain feature is separated from the gate structure by the first dielectric sidewall structure and the second dielectric sidewall structure (US 11527533 B2, claim 1, column 10 lines 17-21), and
wherein the first dielectric sidewall structure includes a different material than the second dielectric sidewall structure (US 11527533 B2, claim 1, column 10 lines 21-23).
Claims 2-4, 6 read on claim 1 of US 11527533 B2.
Regarding claim 8, claim 12 of US 11527533 B2 teaches a semiconductor structure comprising:
a first fin-shaped structure and a second fin-shaped structure (US 11527533 B2, claim 12, column 10 lines 61-62);
a gate structure disposed over the first fin-shaped structure and the second fin-shaped structure (US 11527533 B2, claim 12, column 11 lines 1-3);
a bottom gate spacer disposed on a bottom portion of a sidewall of the gate structure and disposed between the first fin-shaped structure and the second fin-shaped structure (US 11527533 B2, claim 12, column 11 lines 4-5); and
a top gate spacer disposed over the bottom gate spacer and on a top portion of the sidewall of the gate structure (US 11527533 B2, claim 12, column 11 lines 6-7),
wherein the bottom gate spacer includes a different material than the top gate spacer (US 11527533 B2, claim 12, column 11 lines 8-10).
Claim 9 reads on claim 8 of US 11527533 B2.
Regarding claim 21, claim 17 of US 11527533 B2 teaches a semiconductor structure, comprising:
a first fin-shaped structure and a second fin-shaped structure (US 11527533 B2, claim 17, column 11 lines 28-29);
a metal gate structure disposed over the first and second fin-shaped structures (US 11527533 B2, claim 17, column 12 lines 5-6);
a source/drain feature connected to the first and second fin-shaped structures (US 11527533 B2, claim 17, column 12 lines 11-17); and
a gate spacer (US 11527533 B2, claim 17, column 12 lines 7-10) disposed along a sidewall of the metal gate structure,
wherein the gate spacer comprises a first portion (US 11527533 B2, claim 17, column 12 lines 7-8) and a second portion (US 11527533 B2, claim 17, column 12 lines 9-10) below the first portion,
wherein the second portion is lower than a top surface of the first and second fin- shaped structure (US 11527533 B2, claim 17, column 12 lines 9-17).
Claims 22-25 read on claim 18 of US 11527533 B2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 23-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2018/0151564 A1).
Regarding claim 21, Lee teaches a semiconductor structure (device in Figs. 10A-10E of Lee), comprising:
a first fin-shaped structure (left fin of the middle two fins 202 in Fig. 10B of Lee) and a second fin-shaped structure (right fin 202 of the middle two fins);
a metal gate structure (230 in Fig. 10B) disposed over the first and second fin-shaped structures;
a source/drain feature (221) connected to the first and second fin-shaped structures; and
a gate spacer (232) disposed along a sidewall of the metal gate structure,
wherein the gate spacer comprises a first portion (portion of spacer 232 that is above the top surface of the fins 202) and a second portion (portion of spacer 232 below the top surface of the two fins) below the first portion,
wherein the second portion is lower than a top surface of the first and second fin- shaped structure (as defined above).
Regarding claim 23, Lee teaches all limitations of the semiconductor structure of claim 21, and further comprising an isolation feature (205 in Fig. 10B of Lee) between bottom portions (portion of fins at the same level with void 269 in Fig. 10C of Lee) of the first and second fin-shaped structures, wherein the metal gate structure and the gate spacer are above the isolation feature (as shown in Fig. 10B of Lee).
Regarding claim 24, Lee teaches all limitations of the semiconductor structure of claim 23, and further comprising a dielectric structure (void 269 in Fig. 10C) adjacent to the second portion and above the isolation feature, wherein the metal gate structure is disposed over the dielectric structure (as shown in Fig. 10B-10C of Lee).
Regarding claim 25, Lee teaches all limitations of the semiconductor structure of claim 21, and also teaches wherein a top surface of the second portion is coplanar with the top surface of the first and second fin-shaped structure (the second portion of the spacers 232 is defined to extend up to the level of the top surface of the fins 202).
Regarding claim 26, Lee teaches all limitations of the semiconductor structure of claim 21, and further comprising a third fin-shaped structure (leftmost fin in Fig. 10B of Lee) spaced apart from the first and second fin-shaped structures, wherein the metal gate structure is further disposed over the third fin-shaped structure (as shown in Fig. 10B), wherein the second portion of the gate spacer comprises a portion (as defined in claim 21 above) between the second and third fin-shaped structures.
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Subramanian et al. (US 2020/0286891 A1).
Regarding claim 21, Subramanian teaches a semiconductor structure (device in Figs. 3A-3G of Subramanian), comprising:
a first fin-shaped structure (left two fins 302 in Fig. 3B of Subramanian) and a second fin-shaped structure (middle two fins 302);
a metal gate structure (230 in Fig. 3F) disposed over the first and second fin-shaped structures;
a source/drain feature (source/drain regions are inherent structure of a transistor and are located next to the gate structure) connected to the first and second fin-shaped structures; and
a gate spacer (stack from 308-316 and 324 in Fig. 3B-3C) disposed along a sidewall of the metal gate structure,
wherein the gate spacer comprises a first portion (316 and 324) and a second portion (308-312) below the first portion,
wherein the second portion is lower than a top surface of the first and second fin- shaped structure (as shown in Fig. 3B of Subramanian).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian, as applied in claim 21 above, and further in view Hafez et al. (US 2019/0304971 A1).
Regarding claim 22, Subramanian teaches all limitations of the semiconductor structure of claim 21, but does not explicitly teach wherein the first and second portions have different compositions.
Subramanian teaches that the spacer 324 is made of silicon nitride (see [0081] of Subramanian).
Hafez teaches a finfet device with a gate endcap isolation structure (950 in Fig. 9A-9C of Hafez). The gate endcap isolation structure comprises: a first dielectric material (lower dielectric portion 952 in Fig. 9B) conforming to a bottom and sides of the dielectric stack; a second dielectric material (954) along a top surface of the dielectric stack; and a third dielectric material (956) in a middle of the dielectric stack. The first dielectric material is made of silicon nitride (952 is the same as layer 928, which is made of silicon nitride, as described in [0086] of Hafez); the second dielectric material is made of hafnium oxide (as described in [0086] of Hafez); the third dielectric material is made of silicon oxide (as described in [0087] of Hafez).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the dielectric stack of Subramanian as according to Hafez. The material choice is a known solution to a known structure in the art.
As incorporated, the second portion of the gate spacer comprises hafnium oxide which is different than the silicon nitride spacer 324, which is part of the first portion.
Claims 8-11, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Hafez.
Regarding claim 8, Subramanian a semiconductor structure comprising:
a first fin-shaped structure (first fin 302 from the right in Fig. 3B of Subramanian) and a second fin-shaped structure (second fin 302 from the right in Fig. 3B of Subramanian);
a gate structure (340 in Fig. 3F) disposed over the first fin-shaped structure and the second fin-shaped structure;
a bottom gate spacer (308 and 310 between the first and second fin as shown in Fig. 3B-3C) disposed on a bottom portion (portion of sidewall of gate 340 between the fins 302, as shown in the right figure of Fig. 3F) of a sidewall of the gate structure (as written, the phrase “disposed on a bottom portion of a sidewall” does not require that the bottom portion must be in contact with the gate structure) and disposed between the first fin-shaped structure and the second fin-shaped structure (as shown in Fig. 3F); and
a top gate spacer (portion of spacers 316-324 adjacent to the gate 340) disposed over the bottom gate spacer and on a top portion (as shown in Fig. 3F) of the sidewall of the gate structure.
But Subramanian does not teach that wherein the bottom gate spacer includes a different material than the top gate spacer (Subramanian teaches that the spacer 324 is made of silicon nitride, see [0081] of Subramanian).
Hafez teaches a finfet device with a gate endcap isolation structure (950 in Fig. 9A-9C of Hafez). The gate endcap isolation structure comprises: a first dielectric material (lower dielectric portion 952 in Fig. 9B) conforming to a bottom and sides of the dielectric stack; a second dielectric material (954) along a top surface of the dielectric stack; and a third dielectric material (956) in a middle of the dielectric stack. The first dielectric material is made of silicon nitride (952 is the same as layer 928, which is made of silicon nitride, as described in [0086] of Hafez); the second dielectric material is made of hafnium oxide (as described in [0086] of Hafez); the third dielectric material is made of silicon oxide (as described in [0087] of Hafez).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the dielectric stack of Subramanian as according to Hafez. The material choice is a known solution to a known structure in the art.
As incorporated, the second portion of the gate spacer comprises hafnium oxide which is different than the silicon nitride spacer 324, which is part of the first portion.
Regarding claim 9, Subramanian in view of Hafez teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein a top surface of the bottom gate spacer is coplanar with a top surface of the first fin-shaped structure (top surface of 312 in Fig. 3B of Subramanian is at the same level as that of the fins 302).
Regarding claim 10, Subramanian in view of Hafez teaches all limitations of the semiconductor structure of claim 8, and further comprising a source/drain feature (S/D regions of the fins 302, as implied in [0047] of Subramanian) disposed over source/drain regions of the first fin-shaped structure and the second fin-shaped structure.
Regarding claim 11, Subramanian in view of Hafez teaches all limitations of the semiconductor structure of claim 8, and also teaches wherein the first fin-shaped structure is spaced apart from the second fin-shaped structure by a first distance (distance between first and second fin, as shown in Fig. 3B of Subramanian); and
wherein the semiconductor structure further comprises:
a third fin-shaped structure (second fin 302 from the left in Fig. 3B of Subramanian) spaced apart from the second fin-shaped structure by a second distance (as shown in Fig. 3B, the third fin is farther away from the second fin than the first fin) greater than the first distance, and
a dielectric structure (stack of 308-310-312 in Fig. 3B) disposed between the second fin-shaped structure and the third fin-shaped structure,
wherein the second fin-shaped structure is sandwiched between the first fin- shaped structure and the third fin-shaped structure (as shown in Fig. 3B of Subramanian).
Regarding claim 13, Subramanian in view of Hafez teaches all limitations of the semiconductor structure of claim 11, and also teaches wherein the dielectric structure includes a first layer (308 in Fig. 3B of Subramanian), a second layer (310) disposed along sidewalls and a bottom surface of the first layer, and a third layer (312) disposed over a top surface of the first layer,
wherein the gate structure is disposed over the dielectric structure (as shown in Fig. 3F of Subramanian), and
wherein top surfaces of the second layer and the third layer are coplanar with a top surface of the bottom gate spacer (as shown in Fig. 3F of Subramanian).
Regarding claim 14, Subramanian in view of Hafez teaches all limitations of the semiconductor structure of claim 11, and also teach semiconductor structure further comprising a first source/drain feature (S/D of the second fin) disposed over the second fin-shaped structure and a second source/drain feature (S/D of the third fin) disposed over the third fin-shaped structure, wherein the first source/drain feature and the second source/drain feature are separated by the dielectric structure (as shown in Fig. 3B of Subramanian).
Allowable Subject Matter
Claims 1-4, 6 would be allowable if rewritten or amended to overcome the double patenting rejections set forth in this Office action.
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 would be allowable if rewritten to overcome the double patenting rejections, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record does not disclose or fairly suggests a semiconductor structure comprising: “a gate structure disposed over a region of the fin-shaped structure and having a sidewall including a lower portion and an upper portion above the lower portion; a first dielectric sidewall structure disposed along the lower portion of the sidewall; a second dielectric sidewall structure disposed along the upper portion of the sidewall and disposed on the first dielectric sidewall structure;” and “wherein the source/drain feature is separated from the gate structure by the first dielectric sidewall structure and the second dielectric sidewall structure, and wherein the first dielectric sidewall structure includes a different material than the second dielectric sidewall structure” along with other limitations of the claim.
Regarding claim 12, the prior art of record does not disclose or fairly suggests a semiconductor structure satisfying “wherein the bottom gate spacer is a first bottom gate spacer; and wherein the semiconductor structure further comprises: a second bottom gate spacer disposed between the second fin-shaped structure and the dielectric structure, and a third bottom gate spacer disposed between the dielectric structure and the third fin-shaped structure, wherein the top gate spacer is disposed over the second bottom gate spacer and the third bottom gate spacer” along with other limitations of claim 11.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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