DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 07/10/2024.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 07/10/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejection – Non-Statutory Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
5. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,087,844.
Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one of ordinary skill in the art at the time of the invention was made that the claims of the Patent recite all claimed limitations of the instant application. The claims of the instant application are merely describing the limitations of the Patent in different ways, and they are obviously anticipated by the claims of the Patent.
See the claimed element mapping below for details:
Pending Claim(s)
Claim(s) of Patent No. US 12,087,844:
A semiconductor device structure, comprising:
a fin structure extending above a dielectric isolation structure disposed over a semiconductor substrate, the fin structure including:
a source region;
a drain region; and
a channel region disposed between the source region and the drain region, wherein an average germanium concentration in a bottom region of the channel region is greater than an average germanium concentration in an upper region of the channel region.
A semiconductor device structure, comprising:
a fin structure extending above a dielectric isolation structure disposed over a silicon substrate, the fin structure including:
a source region;
a drain region; and
a channel region disposed between the source region and the drain region, wherein an average germanium concentration in a bottom region of the channel region is different from an average germanium concentration in an upper region of the channel region (note: germanium concentration difference can obviously be greater or smaller),
and wherein a threshold voltage of the fin structure is uniform across a height of the fin structure.
2. The semiconductor device structure of claim 1, wherein the upper region of the channel region includes a nonuniform germanium concentration.
7. The semiconductor device structure of claim 1, wherein the upper region of the channel region includes a nonuniform germanium concentration.
3. The semiconductor device structure of claim 1, wherein the upper region of the channel region includes a peripheral region and a central region surrounded by the peripheral region; and
the central region is substantially free of germanium.
8. The semiconductor device structure of claim 1, wherein the upper region of the channel region includes a peripheral region and a central region surrounded by the peripheral region; and
the central region is substantially free of germanium.
4. The semiconductor device structure of claim 1, wherein a difference between the average germanium concentration, expressed as a percentage, in the bottom region of the channel region and the average germanium concentration, expressed as a percentage, in the upper region of the channel region is in a range from about 3% to about 10%.
2. The semiconductor device structure of claim 1, wherein a difference between the average germanium concentration, expressed as a percentage, in the bottom region of the channel region and the average germanium concentration, expressed as a percentage, in the upper region of the channel region is in a range from about 3% to about 10%.
5. The semiconductor device structure of claim 1, further comprising a gate structure over the channel region of the fin structure, the gate structure including a gate dielectric layer conformally lining the channel region of the fin structure and a gate electrode disposed over the gate dielectric layer,
wherein a threshold voltage of the fin structure is uniform across a height of the fin structure.
3. The semiconductor device structure of claim 1, further comprising a gate structure over the channel region of the fin structure, the gate structure including a gate dielectric layer conformally lining the channel region of the fin structure and a gate electrode disposed over the gate dielectric layer.
(from claim 1) wherein a threshold voltage of the fin structure is uniform across a height of the fin structure.
6. The semiconductor device structure of claim 1, wherein the channel region further includes a base region extending from the semiconductor substrate;
the base region of the channel region is laterally surrounded by the dielectric isolation structure; and the base region of the channel region is free of germanium.
4. The semiconductor device structure of claim 1, wherein the channel region further includes a base portion extending from the silicon substrate;
the base portion of the channel region is laterally surrounded by the dielectric isolation structure; and the base portion of the channel region is free of germanium.
7. The semiconductor device structure of claim 1, further comprising a dielectric fin disposed on the semiconductor substrate and configured next to the fin structure.
5. The semiconductor device structure of claim 4, further comprising a dielectric fin disposed on the silicon substrate and configured next to the fin structure.
8. The semiconductor device structure of claim 7, wherein the dielectric fin is laterally surrounded by the dielectric isolation structure; and
the dielectric isolation structure extends to be interposed between the semiconductor substrate and the dielectric fin.
6. The semiconductor device structure of claim 5, wherein the dielectric fin is laterally surrounded by the dielectric isolation structure; and
the dielectric isolation structure further extends to be interposed between the silicon substrate and the dielectric fin.
9. The semiconductor device structure of claim 1, wherein the source region, the drain region, and the channel region are components of a p-type field effect transistor; and
the source region and the drain region include silicon germanium doped with boron (SiGeB) and further include tin.
9. The semiconductor device structure of claim 1, wherein the source region, the drain region, and the channel region are components of a p-type field effect transistor.
10. The semiconductor device structure of claim 9, wherein the source region and the drain region include silicon germanium doped with boron (SiGeB).
11. The semiconductor device structure of claim 10, wherein the source region and the drain region further include tin.
10. A semiconductor device structure, comprising:
a dielectric isolation structure disposed over a substrate; and
a first fin structure and a second fin structure separated by and extending above the dielectric isolation structure, wherein
the first fin structure includes a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region,
the first channel region includes a base portion, a bottom portion and an upper portion with a nonuniform concentration, and
an average germanium concentration in the bottom portion of the first channel region is different from an average germanium concentration in the upper portion of the first channel region, and
wherein the upper portion of the first channel region includes a nonuniform germanium concentration.
12. A semiconductor device structure, comprising:
a semiconductor substrate;
a dielectric isolation structure disposed over the semiconductor substrate; and
a first fin structure and a second fin structure separated by and extending above the dielectric isolation structure, wherein
the first fin structure includes a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region,
the first channel region includes a base portion, a bottom portion and an upper portion with a nonuniform concentration, and
an average germanium concentration in the bottom portion of the first channel region is greater than an average germanium concentration in the upper portion of the first channel region (see further claim 13), and
wherein a threshold voltage of the first fin structure is uniform across a height of the first fin structure.
17. The semiconductor device structure of claim 12, wherein the upper portion of the first channel region further includes a peripheral region and a central region surrounded by the peripheral region; and the central region is substantially free of germanium.
11. The semiconductor device structure of claim 10, wherein the upper portion of the first channel region further includes a peripheral region and a central region surrounded by the peripheral region; and the central region is substantially free of germanium.
17. The semiconductor device structure of claim 12, wherein the upper portion of the first channel region further includes a peripheral region and a central region surrounded by the peripheral region; and the central region is substantially free of germanium.
12. The semiconductor device structure of claim 10, wherein a threshold voltage of the first fin structure is uniform across a height of the first fin structure; and
a difference between the average germanium concentration, expressed as a percentage, in the bottom portion of the first channel region and the average germanium concentration, expressed as a percentage, in the upper portion of the first channel region is in a range from about 3% to about 10%.
(from claim 10) a semiconductor device... wherein a threshold voltage of the first fin structure is uniform across a height of the first fin structure.
13. The semiconductor device structure of claim 12, wherein a difference between the average germanium concentration, expressed as a percentage, in the bottom portion of the first channel region and the average germanium concentration, expressed as a percentage, in the upper portion of the first channel region is in a range from about 3% to about 10%.
13. The semiconductor device structure of claim 10, further comprising a first gate structure over the first channel region of the first fin structure, the first gate structure including a first gate dielectric layer conformally lining the first channel region of the first fin structure and a first gate electrode disposed over the first gate dielectric layer.
14. The semiconductor device structure of claim 12, further comprising a first gate structure over the first channel region of the first fin structure, the first gate structure including a first gate dielectric layer conformally lining the first channel region of the first fin structure and a first gate electrode disposed over the first gate dielectric layer.
14. The semiconductor device structure of claim 10, wherein the first channel region further includes a base portion extending from the substrate;
the base portion of the first channel region is laterally surrounded by the dielectric isolation structure; and
the base portion of the first channel region is free of germanium.
15. The semiconductor device structure of claim 12, wherein the first channel region further includes a base portion extending from the semiconductor substrate;
the base portion of the first channel region is laterally surrounded by the dielectric isolation structure; and
the base portion of the first channel region is free of germanium.
15. The semiconductor device structure of claim 10, further comprising a dielectric fin disposed on the semiconductor substrate and configured next to the first fin structure, wherein the substrate is a silicon substrate, the dielectric fin is laterally surrounded by the dielectric isolation structure, and the dielectric isolation structure further extends to be interposed between the silicon substrate and the dielectric fin.
16. The semiconductor device structure of claim 12, further comprising a dielectric fin disposed on the semiconductor substrate and configured next to the first fin structure, wherein the dielectric fin is laterally surrounded by the dielectric isolation structure, and the dielectric isolation structure further extends to be interposed between the semiconductor substrate and the dielectric fin.
16. The semiconductor device structure of claim 10, wherein the second fin structure includes a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region;
the first source region, the first drain region, and the first channel region are components of a p-type field effect transistor;
the second source region, the second drain region, and the second channel region are components of a n-type field effect transistor; and the second channel region is free of germanium.
18. The semiconductor device structure of claim 12, wherein the second fin structure includes a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region;
the first source region, the first drain region, and the first channel region are components of a p-type field effect transistor;
the second source region, the second drain region, and the second channel region are components of a n-type field effect transistor; and the second channel region is free of germanium.
17. The semiconductor device structure of claim 16, wherein the first source region and the first drain region include silicon germanium doped with tin and boron; and
the second source region and the second drain region include silicon carbide doped with phosphorous.
19. The semiconductor device structure of claim 18, wherein the first source region and the first drain region include silicon germanium doped with tin and boron; and
the second source region and the second drain region include silicon carbide doped with phosphorous.
18. A semiconductor device structure, comprising:
a fin structure extending above a dielectric isolation structure disposed over a silicon substrate, the fin structure including:
a source region;
a drain region; and
a channel region disposed between the source region and the drain region, wherein
an average germanium concentration in a bottom portion of the channel region is different from an average germanium concentration in an upper portion of the channel region, and
the upper portion of the channel region includes a nonuniform germanium concentration.
20. A semiconductor device structure, comprising:
a fin structure extending above a dielectric isolation structure disposed over a silicon substrate, the fin structure including:
a source region;
a drain region; and
a channel region disposed between the source region and the drain region, wherein
an average germanium concentration in a bottom region of the channel region is different from an average germanium concentration in an upper region of the channel region,
a threshold voltage of the fin structure is uniform across a height of the fin structure, and the source region and the drain region include silicon germanium doped with tin and boron.
19. The semiconductor device structure of claim 18, wherein a threshold voltage of the fin structure is uniform across a height of the fin structure; and
the source region and the drain region include silicon germanium doped with tin and boron.
(from claim 20) A semiconductor device structure comprising... a threshold voltage of the fin structure is uniform across a height of the fin structure, and
the source region and the drain region include silicon germanium doped with tin and boron.
20. The semiconductor device structure of claim 18, wherein the upper portion of the channel region includes a peripheral region and a central region surrounded by the peripheral region; and the central region is substantially free of germanium.
17. The semiconductor device structure of claim 12, wherein the upper portion of the first channel region further includes a peripheral region and a central region surrounded by the peripheral region; and the central region is substantially free of germanium.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-2, 10, and 18 are rejected under 35 U.S.C. 102(a)() as being anticipated by Ching et al. (US 2015/0108544)
Regarding claim 1, Ching discloses a semiconductor device structure, comprising:
a fin structure 24 (see Figs. 5-6) extending above a dielectric isolation structure 22 disposed over a semiconductor substrate 20, the fin structure 20 including:
a source region (para. 0021);
a drain region; and
a channel region (covered by gate structure 32, Fig. 6) disposed between the source region and the drain region,
wherein an average germanium concentration in a bottom region 24A of the channel region is greater than an average germanium concentration in an upper region 24B (the upper region can also include a thin portion of layer 24A proximate to the interface between layer 24A and layer 24B) of the channel region. See para. 0010.
Regarding claim 2, Ching discloses the semiconductor device structure of claim 1, wherein the upper region of the channel region includes a nonuniform germanium concentration (germanium concentration changing around the interface between layers 24A and 24B). See para. 0010.
Regarding claim 10, Ching discloses a semiconductor device structure, comprising:
a dielectric isolation structure 22 (see Figs. 5-6) disposed over a substrate; and
a first fin structure 24 and a second fin structure 24 separated by and extending above the dielectric isolation structure 22,
wherein the first fin structure 24 includes a first source region, a first drain region, and a first channel region (para. 0021) disposed between the first source region and the first drain region, the first channel region includes a base portion (protruding from a substrate 20), a bottom portion 24A (or lower portion of layer 24A) and an upper portion 24B (the upper region can also include a thin portion of layer 24A proximate to the interface between layer 24A and layer 24B) with a nonuniform concentration (germanium concentration changing around the interface between layers 24A and 24B), and an average germanium concentration in the bottom portion 24A of the first channel region is different from an average germanium concentration in the upper portion 24B of the first channel region (para. 0010), and wherein the upper portion of the first channel region includes a nonuniform germanium concentration (germanium concentration changing around the interface between layers 24A and 24B).
Regarding claim 18, Ching discloses a semiconductor device structure, comprising:
a fin structure 24 extending above a dielectric isolation structure 22 disposed over a silicon substrate 20, the fin structure including:
a source region (see para. 0010);
a drain region; and
a channel region disposed between the source region and the drain region,
wherein an average germanium concentration in a bottom portion 24A of the channel region is different from an average germanium concentration in an upper portion 24B (the upper region can also include a thin portion of layer 24A proximate to the interface between layer 24A and layer 24B) of the channel region, and
the upper portion of the channel region includes a nonuniform germanium concentration (germanium concentration changing around the interface between layers 24A and 24B).
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 August 31, 2026
Prosecution Insights