DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/10/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seok (KR 10-2018-0065071)
Regarding claim 1, Seok teaches a semiconductor structure in fig. 6, comprising:
a first source/drain feature (refer to a first left 114 of a left transistor 106) and a second source/drain feature (refer to right 114 of a right transistor 106);
a first metal line (126b) electrically connected to the first source/drain feature (refer to the first left 114 of a left transistor 106);
a second metal line (refer to right 124) electrically connected to the second source/drain feature (refer to right 114 of a right transistor 106);
a first memory element (ME) electrically connected to the first source/drain feature by way of the first metal line;
a second memory element (refer to ME) electrically coupled to the second source/drain feature by way of the second metal line; and
a conductive layer (150) extending from a top surface of the first memory element to a top surface of the second memory element.
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Regarding claim 8, Seok teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Seok teaches the first memory element (ME) includes a magneto-resistive random-access memory cell comprising: a first bottom electrode (BE) electrically connected to the first metal line (refer to 124); a first storage material layer (MTJ) disposed over the first bottom electrode (BE); and a first top electrode (UE) disposed over the first storage material layer (MTJ).
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Regarding claim 9, Seok teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Seok teaches the second memory element includes a magneto-resistive random-access memory cell comprising: a second bottom electrode (UE) electrically connected to the second metal line (124); a second storage material layer (MTJ) disposed over the second bottom electrode (BE); and a second top electrode (UE) disposed over the second storage material layer (MTJ), wherein the conductive layer (150) extends from the first top electrode (UE) to the second top electrode (UE).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Seok (KR-10-2018-0065071) as applied to claim 1 above, and further in view of Sakamoto (US 20150270271).
Regarding claim 2, Seok teaches all the limitations of the claimed invention for the same reasons as set forth above except for a channel region coupled to the first source/drain feature; a third source/drain feature coupled to the channel region and disposed between the first source/drain feature and the second source/drain feature in a first direction; and a third metal line electrically coupled to the third source/drain feature and placed at a same level with the first metal line, wherein, in the first direction, a width of the third metal line is greater than a width of the first metal line.
Sakamoto teaches the same field of an endeavor wherein a channel region (refer to the channel region of the left G1) coupled to the first source/drain feature (refer to the left DR1); a third source/drain feature (refer to the middle DR1 region) coupled to the channel region (refer to the channel region of the left TR1) and disposed between the first source/drain feature (refer to the left DR1) and the second source/drain feature (refer to the far right DR1) in a first direction (refer to x-axis direction); and a third metal line (refer to BL) electrically coupled to the third source/drain feature (refer to middle DR1) and placed at a same level with the first metal line (refer to PLGC), wherein, in the first direction, a width of the third metal line (refer to BL) is greater than a width of the first metal line (refer to PLGC) (see fig. 10).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a channel region coupled to the first source/drain feature; a third source/drain feature coupled to the channel region and disposed between the first source/drain feature and the second source/drain feature in a first direction; and a third metal line electrically coupled to the third source/drain feature and placed at a same level with the first metal line, wherein, in the first direction, a width of the third metal line is greater than a width of the first metal line as taught by Sakamoto in the teaching of Seok because the PLGC is to provide short vertical electrical connection from the source/drain electrode to the capacitor’s lower electrodes while the BL needs more area for routing and resistance.
Regarding claim 3, Seok and Sakamoto teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 10 of Sakamoto teaches the second metal line (refer to PLGD) is placed at the same level with the first metal line (refer to PLGC), and in the first direction, a width of the second metal line is equal to the width of the first metal line (see fig. 10).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12063790 in view of Seok (KR-10-2018-0065071).
Regarding claim 1 of the pending application, US Patent teaches a semiconductor structure (see claim 1’s preamble), comprising:
a first source/drain feature and a second source/drain feature (see col. 15, lines 13-14);
a first metal line electrically connected to the first source/drain feature (see col. 15, lines 15-16);
a second metal line electrically connected to the second source/drain feature (see col. 15, lines 17-19);
a first memory element electrically connected to the first source/drain feature by way of the first metal line (See col. 15, lines 20-22);
a second memory element electrically coupled to the second source/drain feature by way of the second metal line (see claim 16); and
US Patent does not mention “a conductive layer extending from a top surface of the first memory element to a top surface of the second memory element.”
Seok teaches the same field of an endeavor wherein a conductive layer (150) extending from a top surface of the first memory element to a top surface of the second memory element (see fig. 6).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a conductive layer extending from a top surface of the first memory element to a top surface of the second memory element as taught by Seok in the teaching of US Patent because the upper conductive line disposed on top of the memory element ME is formed into an extended design rule than the lower conductive patterns 124 and 134 disposed below the memory element ME. Accordingly, it is possible to form the memory element ME while minimizing a change in the logic process (for example, the wiring formation process of the logic structure). In addition, it is possible to prevent defects that may occur during the formation of the memory element ME without additional processing.
Claims 2-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12063790 in view of Seok (KR-10-2018-0065071) as applied to claim 1 above, and further in view of Sakamoto (US 20150270271).
Regarding claim 2 of the pending application, US Patent and Seok teach similar features except for a channel region coupled to the first source/drain feature; a third source/drain feature coupled to the channel region and disposed between the first source/drain feature and the second source/drain feature in a first direction; and a third metal line electrically coupled to the third source/drain feature and placed at a same level with the first metal line, wherein, in the first direction, a width of the third metal line is greater than a width of the first metal line.
Sakamoto teaches the same field of an endeavor wherein a channel region (refer to the channel region of the left G1) coupled to the first source/drain feature (refer to the left DR1); a third source/drain feature (refer to the middle DR1 region) coupled to the channel region (refer to the channel region of the left TR1) and disposed between the first source/drain feature (refer to the left DR1) and the second source/drain feature (refer to the far right DR1) in a first direction (refer to x-axis direction); and a third metal line (refer to BL) electrically coupled to the third source/drain feature (refer to middle DR1) and placed at a same level with the first metal line (refer to PLGC), wherein, in the first direction, a width of the third metal line (refer to BL) is greater than a width of the first metal line (refer to PLGC) (see fig. 10).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a channel region coupled to the first source/drain feature; a third source/drain feature coupled to the channel region and disposed between the first source/drain feature and the second source/drain feature in a first direction; and a third metal line electrically coupled to the third source/drain feature and placed at a same level with the first metal line, wherein, in the first direction, a width of the third metal line is greater than a width of the first metal line as taught by Sakamoto in the teaching of Seok and US Patent because the PLGC is to provide short vertical electrical connection from the source/drain electrode to the capacitor’s lower electrodes while the BL needs more area for routing and resistance.
Regarding claim 3, US Patent, Seok and Sakamoto teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 10 of Sakamoto teaches the second metal line (refer to PLGD) is placed at the same level with the first metal line (refer to PLGC), and in the first direction, a width of the second metal line is equal to the width of the first metal line (see fig. 10).
Claim 10-12,14 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9, 11,13 and 14 of U.S. Patent No. 12063790 in view of Choi (US
Regarding claim 10 of the pending application, US Patent teaches a semiconductor structure (see claim 9’s preamble) comprising:
a memory cell region comprising (see col. 16, line 11):
a first source/drain feature and a second source/drain feature (see lines 12-13), a first metal line electrically connected to the first source/drain feature, and a second metal line electrically connected to the second source/drain feature (see lines 14-19) and having a width different than a width of the first metal line (see claim 11); and
a logic region (see line 24) comprising:
a third metal line electrically connected to the source feature, and a fourth metal line electrically connected to the drain feature and having a width equal to a width of the third metal line (see col. 16, lines 26-30).
US Patent does not mention the memory cell region comprising a first transistor and the logic region comprising: a second transistor comprising a source feature and a drain feature.
Choi teaches the same field of an endeavor wherein memory cell region comprising a first transistor and the logic region comprising: a second transistor comprising a source feature and a drain feature (see fig. 1).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include memory cell region comprising a first transistor and the logic region comprising: a second transistor comprising a source feature and a drain feature as taught by Choi in the teaching of US Patent so that it integrates logic and memory on a single IC chip.
Regarding claim 11 of the pending application, claim 11 of US Patent and choi teaches similar features of claim 11.
Regarding claim 12 of the pending application, claim 11 of US Patent and choi teaches similar features of claim 12.
Regarding claim 14 of the pending application, claim 13 of US Patent and choi teaches similar features of claim 14.
Regarding claim 15 of the pending application, claim 14 of US Patent and choi teaches similar features of claim 14.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “… the first metal line and the third metal line extend lengthwise along a second direction substantially perpendicular to the first direction, and a length of the first metal line is less than a length of the third metal line” in combination of the other limitations of claim 4.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest a transistor including a source feature and a drain feature; a fourth metal line electrically connected to the source feature and placed at the same level with the first metal line, and a fifth metal line electrically connected to the drain feature and placed at the same level with the first metal line, wherein a width of the fourth metal line is substantially equal to a width of the fifth metal line and is greater than the width of the first metal line” in combination of the other limitations of claim 5. Claims 6-7 include all of the limitations of claim 5.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “… a length of the first metal line is less than a length of the second metal line” in combination of the other limitations of claim 13.
Regarding claim 16, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a semiconductor structure, comprising “wherein the second metal line having a second width along the second direction and a second length along the first direction, the second width is different from the first width, and the second length is different from the first length” in combination of all of the limitations of claim 16. Claims 17-20 include all of the limitations of claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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