DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6, 8-10, and 12-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12, 087, 834. Although the claims at issue are not identical, they are not patentably distinct from each other because clams 1-20 of the present Application are anticipated or obvious by claims 1-20 of U.S. Patent No. 12, 087, 834.
Present Application
US Patent 12, 087, 834
Claim 1
Claims 1, 3, 16
Claim 2
Claim 4
Claim 3
Claim 18
Claim 4
Claim 3
Claims 5, 6
Claims 5, 6
Claim 8
Claim 7
Claims 9, 10
Claims 8, 9
Claims 12
Claim 10
Claim 13
Claims 16-8
Claims 14-17
Claims 1, 16, 18, 19
Claim 18-20
Claims 16-20
Claims 7 and 11 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12, 087, 834 in view of Choi (US 2016/0233164).
Although claims 1-20 of US 2016/0233164 does not disclose that the glue layer comprises the glue layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof and he silicide layer comprises cobalt silicide, titanium silicide, nickel silicide, copper silicide, tungsten silicide, molybdenum silicide, or a combination thereof, Choi discloses the glue layer (130) comprises titanium ([0059]) and wherein the silicide layer (140) comprises titanium silicide ([0059]).
It would have been therefore obvious to one of ordinary skill in the art at the art to use the above materials for glue layer and the silicide layer because it is typical materials for fabrication glue layers and silicide layers.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11, and 17-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Choi (US 2016/0233164).
Regarding claim 1, Choi discloses a semiconductor device, comprising: a source/drain structure (Fig.13A, numeral 120); a contact structure (Fig.15A, numeral 160P) over the source/drain structure (120); a glue layer (130) surrounding the contact structure (160P); a barrier layer (170) formed on at least a portion of a sidewall surface of the contact structure (160); and a silicide layer (140) between the source/drain structure (120) and the contact structure (160P) and in direct contact with the glue layer (130), wherein a bottom surface of the glue layer (130) is lower than a top surface of the source/drain structure (120) and a bottom surface of the barrier layer (170) (Fig. 17).
Regarding claim 2, Choi discloses wherein the bottom surface of the glue layer (130) is between the bottom surface of the barrier layer (170) and a bottom surface of the source/drain structure (120).
Regarding claim 3, Choi discloses wherein a length of the glue layer (130) is different from a length of the barrier layer (170).
Regarding claim 4, Choi discloses wherein the silicide layer (140) completely covers the bottom surface of the glue layer (130).
Regarding claim 5, Choi discloses wherein a band gap value of the glue layer is less than a band gap value of the barrier layer (note: (130) is titanium [0059]; (170) is silicon nitride; [0147]).
Regarding claim 6, Choi discloses wherein a band gap value of the barrier layer (170) is in a range from about 4eV to about 9eV (note: silicon nitride band gap value is 5eV ; [0147]).
Regarding claim 7, Choi discloses wherein the glue layer (130) comprises titanium ([0059]).
Regarding claim 8, Choi discloses wherein the barrier layer (170) comprises silicon nitride ([0147]).
Regarding claim 11, Choi discloses wherein the silicide layer (140) comprises titanium silicide ([0059]).
Regarding claim 17, Choi discloses a semiconductor device, comprising: a source/drain structure (Fig.17, numeral 120); a dielectric layer (136) ; (132) over the source/drain structure (120); a contact structure (160) passing through the dielectric layer (136); (132); a glue layer (Fig.15B, numeral 130) between the dielectric layer (132); (136) and the contact structure (160) and formed on a bottom surface and a sidewall surface of the contact structure (160); a barrier layer (Fig.17, numeral 170) between the dielectric layer (132); (136) and the contact structure (160) and formed on the sidewall surface of the contact structure (160) (Fig.17); a silicide layer (140) between the source/drain structure (120) and the barrier layer (170), wherein a bottom surface of the barrier layer (170) is between a top surface of the source/drain structure (120) and a bottom surface of the source/drain structure (120), and the bottom surface of the barrier layer (170) is misaligned with a bottom surface of the glue layer (130) (Fig. 15B; Fig.17).
Regarding claim 18, Choi discloses wherein a top surface of the silicide layer (140) is lower than the bottom surface of the barrier layer (170) (Fig.17).
Regarding claim 19, Choi discloses wherein the contact structure (160) is spaced apart from the silicide layer (140) by the glue layer (130) (Fig.15B).
Regarding claim 20, Choi discloses a gate structure (Fig.17, GL) adjacent to the source/drain structure (120), wherein the barrier layer (170) comprises a first part and a second part separated from each other, a top surface of the first part (upper part of (170)) is leveled with the contact structure (160) (Fig. 17), and a top surface of the second part (middle part of (170)) is leveled with the gate structure (GL).
Claims 13-15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Hsieh (US 2016/0071799).
Regarding claim 13, Hsieh discloses a semiconductor device, comprising: a source/drain structure (Fig.1 numeral 120); a dielectric layer (140) over the source/drain structure (120); a contact structure (190) passing through the dielectric layer (140); a silicide layer (180) over the source/drain structure (120); a glue layer (170) between the dielectric layer (140) and the contact structure (190); and a barrier layer (160) between the dielectric layer (140) and the glue layer (170), wherein a portion of the glue layer (170) and an entirety of the silicide layer (180) are embedded in the source/drain structure (190), and a top surface of the source/drain structure (120) is spaced apart from a top surface of the silicide layer (180) (Fig.1).
Regarding claim 14, Hsieh discloses wherein the silicide layer (180) is in direct contact with a bottom surface of the glue layer (170) (note: (180) is in direct contact with (170); “a bottom surface “is not defined, any surface could be considered as “a bottom surface”).
Regarding claim 15, Hsieh discloses wherein a bottom surface of the barrier layer (160) is located at a first level, and a bottom surface of the contact structure (190) is located at a second level, and the first level is different from the second level (Fig.1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2014/0346575) in view of Hsieh.
Regarding claim 1, Chen discloses a semiconductor device, comprising: a source/drain structure (Fig.8, numeral 30a); a contact structure (110B) over the source/drain structure (30a); a glue layer (112) surrounding the contact structure (30a); a barrier layer (28) formed on at least a portion of a sidewall surface of the contact structure (30a);, wherein a bottom surface of the glue layer (112) is lower than a top surface of the source/drain structure (30a) and a bottom surface of the barrier layer (28).
Chen does not disclose a silicide layer between the source/drain structure and the contact structure and in direct contact with the glue layer.
Hsieh however discloses a silicide layer (Fig.1, numeral 180) between the source/drain structure (120) and the contact structure (190) and in direct contact with the glue layer (170).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen with Hsieh to have a silicide layer between the source/drain structure and the contact structure and in direct contact with the glue layer for the purpose of reducing contact resistance (Hsieh, [0001])
Regarding claim 12, Chen discloses a gate structure (Fig.8, 20a) adjacent to the source/drain structure (30a), wherein the glue layer (112) comprises a first outermost sidewall directly over the source/drain structure (30a) and a second outermost sidewall directly over the gate structure (20a).
Regarding claim 13, Chen discloses a semiconductor device, comprising: a source/drain structure (Fig.8, numeral 30a); a dielectric layer (60) over the source/drain structure (30a); a contact structure (110b) passing through the dielectric layer (60); a glue layer (112) between the dielectric layer (60) and the contact structure (30a); and a barrier layer (28) between the dielectric layer (60) and the glue layer (112), wherein a portion of the glue layer (112) is embedded in the source/drain structure (30a),
Chen does not disclose a silicide layer over the source/drain structure and that an entirety of the silicide layer is embedded in the source/drain structure and a top surface of the source/drain structure is spaced apart from a top surface of the silicide layer.
Hsieh however discloses a silicide layer (Fig.1, numeral 180) over the source/drain structure (120) and that an entirety of the silicide layer (180) is embedded in the source/drain structure (120) and a top surface of the source/drain structure (120) is spaced apart from a top surface of the silicide layer (180).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Chen with Hsieh to a silicide layer over the source/drain structure and that an entirety of the silicide layer is embedded in the source/drain structure and a top surface of the source/drain structure is spaced apart from a top surface of the silicide layer for the purpose of reducing contact resistance (Hsieh, [0001]).
Regarding claim 16, Chen discloses a gate structure (Fig. 8, numeral 20a) adjacent to the source/drain structure (30a), wherein the glue layer (112) comprises a first part directly over the source/drain structure (30a) and a second part directly over the gate structure (20a).
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 1 above, and further in view of Grill (US 2014/0256153).
Regarding claims 9 and 10, Choi does not disclose that the barrier layer comprises fluorine within, wherein a concentration of the fluorine in the barrier layer is in a range from about 2at% to about 4at%.
Choi however discloses that the barrier layer is silicon nitride ([0147]). And Grill discloses adding fluorine (F) to the silicon nitride barrier layer to achieve desirable film properties ([0046)).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Choi with Grill to have the barrier layer comprises fluorine (F) within, wherein a concentration of the fluorine (F) in the barrier layer is in a range from about 2at% to about 4at% for the purpose of achieving desirable film properties.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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