DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8 and 10 objected to because of the following informalities. Claim 8 contains duplicate commas at the end of line 3 of the claim. Claim 10 contains the phrase, “wherein the raw materials comprises a raw material,” in line 1 of the claim. For the purpose of this office action, this phrase is interpreted to have the following meaning: wherein the raw materials comprise a raw material. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation, “selectively etching a top portion of one or more of the first spacer layer, the sacrificial spacer layer, and the second spacer layer,” in lines 8-9 of the claim. It is unclear whether the limitation is referring to selectively etching a top portion of one or more of the first spacer layer or the sacrificial spacer layer and also selectively etching a top portion of the second spacer layer, or if the limitation is referring to selectively etching a top portion of one or more of the first spacer layer, the sacrificial spacer layer, or the second spacer layer. The meets and bounds of claim 13 are unclear because of a lack of clarity between the phrase, “one or more of,” and the phrase, “and the second spacer layer”. For the purpose of this office action, the above quoted limitation of lines 8-9 of claim 11 is interpreted to have the following meaning: selectively etching a top portion of one or more of the first spacer layer, the sacrificial spacer layer, or the second spacer layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PGPub 20190296123 A1; hereinafter referred to as "Lee”).
Re claim 1: Lee teaches a method, comprising: forming an intermediate spacer structure (FIG. 1, 6: el. 22, 24, 26; para. 31) between a gate capping structure (FIG. 6: el. 40; para. 50) and a source/drain (S/D) contact structure (FIG. 6: el. 42; para. 53), wherein the intermediate spacer structure comprises: a first spacer layer (FIG. 6: el. 22) in contact with a first sidewall of the gate capping structure (FIG. 6: el. 22, 40), a second spacer layer (FIG. 6: el. 26) in contact with a second sidewall of the S/D contact structure (FIG. 6: el. 26, 42), and a sacrificial spacer layer (FIG. 1: el. 24, FIG. 6: el. 24’; para. 36) between the first and second spacer layers (FIG. 1: el. 22, 24, 26); removing a top portion of the intermediate spacer structure (FIG. 7; para. 54-55); removing the sacrificial spacer layer to form an air gap (FIG. 8: el. 44; para. 56-57) between the first spacer layer and the second spacer layer (FIG. 8); and forming a dielectric structure (FIG. 9: el. 46) on the first and second spacer layers to seal the air gap (FIG. 9: el. 46, 22, 26; para. 58-60), wherein the dielectric structure is in contact with at least one of the first sidewall and the second sidewall (FIG. 9: el. 46, 42).
Re claim 13: Lee teaches a method, comprising: forming a first spacer layer (FIG. 6: el. 22; para. 31) on a sidewall of a gate capping structure (FIG. 6: el. 22, 40); forming a sacrificial spacer layer (FIG. 1: el. 24; para. 31; FIG. 6: el. 24’; para. 36) in contact with the first spacer (FIG. 1: el. 24, 22); forming a second spacer layer (FIG. 6: el. 26; para. 31) in contact with the sacrificial spacer layer (FIG. 1: el. 24, 26); forming a source/drain (S/D) contact structure (FIG. 6: el. 42; para. 53) in contact with the second spacer layer (FIG. 6: el. 42, 26; para. 31|in contact with the contact structure 42 through the liner 34), wherein the first spacer layer, the sacrificial spacer layer, or the second spacer layer are between the S/D contact structure and the gate capping structure (FIG. 6: el. 22, 24’, 26, 42, 40); selectively etching a top portion of one or more of the first spacer layer, the sacrificial spacer layer, and the second spacer layer (FIG. 7; para. 54-55); removing the sacrificial spacer layer to form an air gap (FIG. 8: el. 44; para. 56-57) between the first spacer layer and the second spacer layer (FIG. 8); and forming a dielectric structure (FIG. 9: el. 46) on the first spacer layer and the second spacer layer to seal the air gap (FIG. 9: el. 46, 22, 26; para. 58-60), wherein the dielectric structure is in contact with at least one of the sidewall of the gate capping structure and a sidewall of the S/D contact structure (FIG. 9: el. 46, 42).
Re claim 14: The method of claim 13, wherein the selectively etching the top portion comprises etching the top portion of the first spacer layer, the second spacer layer, and the sacrificial spacer layer (FIG. 7; para. 54-55).
Re claim 15: The method of claim 13, wherein the selectively etching the top portion comprises etching the top portion of the first spacer layer and the sacrificial spacer layer (FIG. 7; para. 54-55).
Re claim 16: The method of claim 13, wherein the selectively etching the top portion comprises etching the top portion of the second spacer layer and the sacrificial spacer layer (FIG. 7; para. 54-55).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Kim et al. (US 9627514 B1; hereinafter referred to as "Kim”) and Zenasni et al. (“Thermal furnace and Ultraviolet assisted curing impact on SiOCH spin-on ultra low dielectric constant materials,” pg. 1097-1103; hereinafter referred to as “Zenasni”).
Re claim 2: Lee teaches the method of claim 1, wherein forming the dielectric structure comprises: forming a dielectric layer on the first spacer layer and the second spacer layer; and polishing the dielectric layer to form the dielectric structure (para. 59; FIG. 9: el. 46). Lee fails to expressly disclose the method of claim 1, wherein forming the dielectric structure comprises: spinning raw materials on the first spacer layer and the second spacer layer; treating the raw materials to form a dielectric layer.
In a similar field of endeavor, Kim teaches forming an air gap between gate and S/D electrodes by forming a dielectric in a recess between the gate and S/D electrodes (FIG. 12B: el. 630; col. 10: line 19-28). Kim further teaches CVD dielectric deposition and spin-on dielectric deposition as equivalent processes for forming a suitable low-k dielectric capping layer (col. 13: line 3-16). It would have been obvious to one of ordinary skill in the art to substitute one known method of forming a dielectric material (CVD gas-phase deposition) for another known equivalent method of forming a dielectric material (spin-on deposition of dielectric raw materials) yielding the predictable result of a suitable low-k dielectric for capping an air gap spacer between gate and S/D electrodes.
The combination of Lee and Kim fails to teach treating the raw materials to form a dielectric layer.
In a similar field of endeavor, Zenasni teaches forming a robust ultra-low dielectric constant spin-on dielectric by spinning on raw materials and UV curing the raw materials (abstract, pg. 1098: column 2: para. 1). Zenasni teaches treating the raw materials to form a dielectric layer (abstract). Zenasni further teaches a benefit of the UV cure treatment of the raw materials of a spin-on dielectric is increased mechanical stability of the dielectric (abstract). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Lee and Kim with the teaching of Zenasni, to enable using the treating of the raw materials of Zenasni in the spin-on dielectric step of the method of Lee and Kim, for the benefit of increased mechanical stability.
Re claim 3: The combination of Lee, Kim, and Zenasni teaches the method of claim 2, wherein the treating the raw materials comprises baking the raw materials at a temperature ranging from about 300 °C to about 700 0C (Zenasni – pg. 1098: column 2: para. 1: sent. 6| Zenasni specifically discloses baking the raw materials at a temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim").
Re claim 4: The combination of Lee, Kim, and Zenasni teaches the method of claim 2, wherein the treating the raw materials comprises performing an ultraviolet (UV) treatment on the raw materials at a temperature ranging from about 100 °C to about 500 °C (Zenasni – pg. 1098: column 2: para. 1: sent. 6| Zenasni specifically discloses performing an ultraviolet treatment on the raw materials at a temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim").
Claims 2, 5-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Kim and Jeong et al. (US 6485815 B1; hereinafter referred to as "Jeong”).
Re claim 2: Lee teaches the method of claim 1, wherein forming the dielectric structure comprises: forming a dielectric layer on the first spacer layer and the second spacer layer; and polishing the dielectric layer to form the dielectric structure (para. 59; FIG. 9: el. 46). Lee fails to expressly disclose the method of claim 1, wherein forming the dielectric structure comprises: spinning raw materials on the first spacer layer and the second spacer layer; treating the raw materials to form a dielectric layer.
In a similar field of endeavor, Kim teaches forming an air gap between gate and S/D electrodes by forming a dielectric in a recess between the gate and S/D electrodes (FIG. 12B: el. 630; col. 10: line 19-28). Kim further teaches CVD dielectric deposition and spin-on dielectric deposition as equivalent processes for forming a suitable low-k dielectric capping layer (col. 13: line 3-16). It would have been obvious to one of ordinary skill in the art to substitute one known method of forming a dielectric material (CVD gas-phase deposition) for another known equivalent method of forming a dielectric material (spin-on deposition of dielectric raw materials) yielding the predictable result of a suitable low-k dielectric for capping an air gap spacer between gate and S/D electrodes.
The combination of Lee and Kim fails to teach treating the raw materials to form a dielectric layer.
In a similar field of endeavor, Jeong teaches forming a low dielectric constant spin-on dielectric with improved adhesion by spinning on raw materials and plasma treating the spin-on dielectric materials (col. 1: line 53-56; col. 2: line 43-54; col. 8: line 50 – col. 9: line 15). Jeong teaches treating the raw materials to form a dielectric layer (col. 9: line 1-15). Jeong further teaches a benefit of plasma treatment of the raw materials of a spin-on dielectric is improved adhesion of subsequent layers formed on the spin-on dielectric (col. 9: line 1-15, col. 2: line 43-54). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Lee and Kim with the teaching of Jeong, to enable using the treating of the raw materials of Jeong in the spin-on dielectric step of the method of Lee and Kim, for the benefit of improved adhesion.
Re claim 5: The combination of Lee, Kim and Jeong teaches the method of claim 2, wherein the treating the raw materials comprises performing an ozone (03) treatment on the raw materials at a temperature ranging from about 10 °C to about 500 °C (Jeong – col. 8: line 50-67, line 4-14| Jeong specifically discloses a treatment temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim"). Jeong specifically discloses the ozone plasma treatment as one of three predictable solutions for improved adhesion. One of ordinary skill in the art would have recognized the finite number of predictable solutions for treatments to improve adhesion of the spin-on dielectric. Absent unexpected results, it would have been obvious to try each of the three plasma treatments to yield a spin-on dielectric with improved adhesion.
Re claim 6: The combination of Lee, Kim and Jeong teaches the method of claim 2, wherein the treating the raw materials comprises performing a plasma treatment on the raw materials at a temperature ranging from about 50 °C to about 500 °C (Jeong – col. 8: line 50-67, line 4-14| Jeong specifically discloses a treatment temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim").
Re claim 7: The combination of Lee, Kim and Jeong teaches the method of claim 2, wherein the treating the raw materials comprises performing an ammonia (NH3) treatment on the raw materials at a temperature ranging from about 50 °C to about 700 °C (Jeong – col. 8: line 50-67, line 4-14| Jeong specifically discloses a treatment temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim"). Jeong specifically discloses the NH3 plasma treatment as one of three predictable solutions for improved adhesion. One of ordinary skill in the art would have recognized the finite number of predictable solutions for treatments to improve adhesion of the spin-on dielectric. Absent unexpected results, it would have been obvious to try each of the three plasma treatments to yield a spin-on dielectric with improved adhesion.
Re claim 9: The combination of Lee, Kim and Jeong teaches the method of claim 2, wherein the raw materials comprise a raw material in the form of Si(OR)4, and wherein R is one of CH3, and C2H5. (Jeong - col. 1: line 53-56; col. 8: line 26 – col. 9: line 3).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim and Zenasni as applied to claim 2 above, and further in view of Kohl et al. (“Low k Porous Methyl Silsesquioxane and Spin-On-Glass,” pg. 77-79; hereinafter referred to as “Kohl”).
Re claim 8: The combination of Lee, Kim, and Zenasni fails to teach the method of claim 2, wherein the raw materials comprise a raw material in the form of Si(R)x(OR')y, and wherein: each of R and R' is one of H, CH3, C2H5, and C3H7, x and y are positive integers, and a sum of x and y is 4.
In a similar field of endeavor, Kohl teaches a spin-on dielectric material, wherein the raw materials comprise a raw material in the form of Si(R)x(OR')y, and wherein: each of R and R' is one of H, CH3, C2H5, and C3H7, x and y are positive integers, and a sum of x and y is 4 (pg. 77: abstract, col. 1|triethoxy silyl groups are of the form of Si(R)x(OR')y, wherein each of R and R' is one of H, CH3, C2H5, and C3H7, x and y are positive integers, and a sum of x and y is 4). Kohl further teaches a benefit of the spin-on dielectric formed from raw materials including triethoxy silyl groups is improved adhesion of the spin-on dielectric to metal and oxide surfaces (pg. 77: para. 2).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Lee, Kim, and Zenasni with the teaching of Kohl, to enable using the spin-on dielectric raw material of Kohl in the method of Lee, Kim, and Zenasni, for the benefit of improved adhesion to metal and oxide surfaces.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Jhan et al. (US PGPub 20190165133 A1; hereinafter referred to as "Jhan”)
Re claim 11: Lee fails to teach the method of claim 1, wherein the dielectric structure comprises carbon in a range from about 2 atomic percent to about 30 atomic percent.
In a similar field of endeavor, Jhan teaches a spacer structure and an ILD layer include SiOCN with different carbon concentrations (para. 21). Jhan further teaches the etching selectivity of the spacer structures and ILD is dependent on and can be tuned by the carbon concentration (para. 21-22). Jhan teaches wherein the dielectric structure comprising carbon in a range from about 2 atomic percent to about 30 atomic percent (para. 21-22|Jhan discloses a dielectric structure comprising carbon in a range of 0 percent to 2 percent or greater than 2 percent and further teaches the carbon concentration of the dielectric layer as a result effective variable for forming a desired selectivity with respect to adjacent layers). In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the concentration of carbon of the dielectric, to achieve the claimed range of about 2 atomic percent to about 30 atomic percent, as a matter of routine optimization.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Lee and Jhan, to enable using the carbon concentration of the dielectric of Jhan in the dielectric structure of the method of Lee, for the benefit of improving selectivity of the dielectric with respect to adjacent layers.
Re claim 12: Lee fails to teach the method of claim 1, wherein the dielectric structure comprises silicon and oxygen, and a ratio between the carbon and the oxygen ranges from about 1.5 to about 3.0.
In a similar field of endeavor, Jhan teaches a spacer structure and an ILD layer include SiOCN with different carbon and oxygen concentrations (para. 21). Jhan further teaches the etching selectivity of the spacer structures and ILD is dependent on and can be tuned by the carbon and oxygen ratio (para. 21-22). Jhan teaches wherein the dielectric structure comprises silicon and oxygen, and a ratio between the carbon and the oxygen ranges from about 1.5 to about 3.0 (para. 21-22|Jhan discloses a spacer dielectric structure comprising a carbon to oxygen ratio of about 2/3 or higher and further teaches the carbon to oxygen ratio as a result effective variable for forming a desired selectivity with respect to adjacent layers). In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the ratio between the carbon and oxygen, to achieve the claimed range of about 1.5 to about 3.0, as a matter of routine optimization.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Lee and Jhan, to enable using the ratio between carbon and oxygen of the dielectric of Jhan in the dielectric structure of the method of Lee, for the benefit of improving selectivity of the dielectric with respect to adjacent layers.
Claims 17, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US PGPub 20190172752 A1; hereinafter referred to as "Hsu”) in view of Kim and Zenasni.
Re claim 17: Hsu teaches a method, comprising: forming an intermediate spacer structure (FIG. 4: el. 28, 34, (58, 60, 62, 64); para. 13-14, 20-21) on sidewalls of a gate structure (FIG. 8: el. 46, 48, 50; para. 15) and a gate capping structure (FIG. 8: el. 44; para. 18), wherein the intermediate spacer structure comprises a first spacer layer (FIG. 4: el. 28; para. 13), a second spacer layer (FIG. 4: el. (58, 60, 62, 64); para. 20-21), and a sacrificial spacer layer (FIG. 4: el. 34; para. 14, 24, 29) between the first and second spacer layers (FIG. 4); forming a source/drain (S/D) contact structure in contact with the second spacer layer (FIG. 8: el. 76, (58, 60, 62, 64); para 27-28|S/D contact structure 76 in contact with second spacer layer 58 through liner 74); selectively etching a top portion of the intermediate spacer structure to form a recess between the gate capping structure and the S/D contact structure (FIG. 9: el. 80; para. 29); removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer (FIG. 9: el. 80; para. 29); forming a dielectric structure in the recess to seal the air gap (FIG. 9: el. 82; para. 29), wherein the dielectric structure is in contact with at least one of the sidewall gate capping structure and a sidewall of the S/D contact structure (FIG. 9: el. 82|dielectric structure 82 formed in the recess 80 is in contact with the sidewall of the S/D contact structure 78 through the remaining portion of the second spacer 58). Hsu is silent on spinning raw materials in the recess to seal the air gap; and treating the raw materials to form a dielectric structure.
In a similar field of endeavor, Kim teaches forming an air gap between gate and S/D electrodes by forming a dielectric in a recess between the gate and S/D electrodes (FIG. 12B: el. 630; col. 10: line 19-28), and teaches forming a dielectric in the recess by CVD deposition and forming a dielectric in the recess by spinning on dielectric raw materials as equivalent processes for forming a suitable low-k dielectric air gap sealing layer (col. 13: line 3-16, col. 10: line 19-28). Also within a similar field of endeavor, Zenasni teaches forming a robust ultra-low dielectric constant spin-on dielectric by spinning on raw materials and UV curing the raw materials (abstract, pg. 1098: column 2: para. 1). Zenasni teaches treating the raw materials to form a dielectric layer (abstract). Zenasni further teaches a benefit of the UV cured spin-on dielectric is an ultra-low dielectric constant alongside mechanical stability (abstract).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Hsu with the teachings of Kim and Zenasni, to enable using the spin-on dielectric step of Kim and Zenasni and the treating of raw materials step of Zenasni in the method of Hsu, for the benefit of a dielectric with an ultra-low dielectric constant alongside mechanical stability.
Re claim 18: The combination of Hsu, Kim, and Zenasni teaches the method of claim 17, wherein the treating the raw materials comprises baking the raw materials at a temperature ranging from about 300 °C to about 700 °C (Zenasni – pg. 1098: column 2: para. 1: sent. 6| Zenasni specifically discloses baking the raw materials at a temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim").
Re claim 19: The combination of Hsu, Kim, and Zenasni teaches the method of claim 17, wherein the treating the raw materials comprises performing an ultraviolet (UV) treatment on the raw materials at a temperature ranging from about 100 °C to about 500 °C (Zenasni – pg. 1098: column 2: para. 1: sent. 6| Zenasni specifically discloses performing an ultraviolet treatment on the raw materials at a temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim").
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Kim and Jeong.
Re claim 17: Hsu teaches a method, comprising: forming an intermediate spacer structure (FIG. 4: el. 28, 34, (58, 60, 62, 64); para. 13-14, 20-21) on sidewalls of a gate structure (FIG. 8: el. 46, 48, 50; para. 15) and a gate capping structure (FIG. 8: el. 44; para. 18), wherein the intermediate spacer structure comprises a first spacer layer (FIG. 4: el. 28; para. 13), a second spacer layer (FIG. 4: el. (58, 60, 62, 64); para. 20-21), and a sacrificial spacer layer (FIG. 4: el. 34; para. 14, 24, 29) between the first and second spacer layers (FIG. 4); forming a source/drain (S/D) contact structure in contact with the second spacer layer (FIG. 8: el. 76, (58, 60, 62, 64); para 27-28|S/D contact structure 76 in contact with second spacer layer 58 through liner 74); selectively etching a top portion of the intermediate spacer structure to form a recess between the gate capping structure and the S/D contact structure (FIG. 9: el. 80; para. 29); removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer (FIG. 9: el. 80; para. 29); forming a dielectric structure in the recess to seal the air gap (FIG. 9: el. 82; para. 29), wherein the dielectric structure is in contact with at least one of the sidewall gate capping structure and a sidewall of the S/D contact structure (FIG. 9: el. 82|dielectric structure 82 formed in the recess 80 is in contact with the sidewall of the S/D contact structure 78 through the remaining portion of the second spacer 58). Hsu is silent on spinning raw materials in the recess to seal the air gap; and treating the raw materials to form a dielectric structure.
In a similar field of endeavor, Kim teaches forming an air gap between gate and S/D electrodes by forming a dielectric in a recess between the gate and S/D electrodes (FIG. 12B: el. 630; col. 10: line 19-28), and teaches forming a dielectric in the recess by CVD deposition and forming a dielectric in the recess by spinning on dielectric raw materials as equivalent processes for forming a suitable low-k dielectric air gap sealing layer (col. 13: line 3-16). Also within a similar field of endeavor, Jeong teaches forming a low dielectric constant spin-on dielectric with improved adhesion by spinning on raw materials and plasma treating the spin-on dielectric materials (col. 1: line 53-56; col. 2: line 43-54; col. 8: line 50 – col. 9: line 15). Jeong teaches treating the raw materials to form a dielectric layer (col. 9: line 1-15). Jeong further teaches a benefit of a spin-on dielectric is a low dielectric constant and a benefit of plasma treatment of the raw materials of a spin-on dielectric is improved adhesion of subsequent layers formed on the spin-on dielectric (col. 9: line 1-15, col. 2: line 43-54).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Hsu with the teachings Kim and Jeong, to enable using the spin-on dielectric step of Kim and Jeong and the treating of raw materials step of Jeong in the method of Hsu, for the benefit of a dielectric with a low dielectric constant alongside improved adhesion.
Re claim 20: The combination of Hsu, Kim, and Jeong teaches the method of claim 17, wherein the treating the raw materials comprises performing an ozone (03) treatment on the raw materials at a temperature ranging from about 10 °C to about 500 °C (Jeong – col. 8: line 50-67, line 4-14| Jeong specifically discloses a treatment temperature of 400 °C, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim"). Jeong specifically discloses the ozone plasma treatment as one of three predictable solutions for improved adhesion. One of ordinary skill in the art would have recognized the finite number of predictable solutions for treatments to improve adhesion of the spin-on dielectric. Absent unexpected results, it would have been obvious to try each of the three plasma treatments to yield a spin-on dielectric with improved adhesion.
Allowable Subject Matter
Claim 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 10: The closest prior art, Lee et al. (US PGPub 20190296123 A1), Kim et al. (US 9627514 B1), Zenasni et al. (“Thermal furnace and Ultraviolet assisted curing impact on SiOCH spin-on ultra low dielectric constant materials”), and Kohl et al. (“Low k Porous Methyl Silsesquioxane and Spin-On-Glass”), either alone or in combination fails to disclose or suggest, “wherein the raw materials comprise a raw material in the form of SiC4H7(OR)3, and wherein R is one of CH3, and C2H5,” in combination with the additionally claimed features, as claimed by the applicant.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 17 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 11626482 (Chen et al.; hereinafter referred to as ‘482).
Instant Application
US 11626482 B2
Claim 17:
A method, comprising: forming an intermediate spacer structure on sidewalls of a gate structure and a gate capping structure, wherein the intermediate spacer structure comprises a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first and second spacer layers;
forming a source/drain (S/D) contact structure in contact with the second spacer layer;
selectively etching a top portion of the intermediate spacer structure to form a recess between the gate capping structure and the S/D contact structure;
removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer;
spinning raw materials in the recess to seal the air gap;
and treating the raw materials to form a dielectric structure,
wherein the dielectric structure is in contact with at least one of the sidewall gate capping structure and a sidewall of the S/D contact structure.
Claim 17:
A method, comprising: forming an intermediate spacer structure on sidewalls of a gate structure and a gate capping structure, wherein the intermediate spacer structure comprises a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first and second spacer layers, and wherein the first spacer layer is in contact with the gate structure and the gate capping structure;
forming a S/D contact structure in contact with the second spacer layer;
selectively etching a top portion of the sacrificial spacer layer and a top portion of at least one of the first spacer layer and the second spacer layer to form a recess between the gate capping structure and the S/D contact structure;
removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer;
depositing a dielectric layer in the recess with a spin-on process to seal the air gap, wherein the dielectric layer comprises raw materials for a spin-on dielectric material;
treating the raw materials in the dielectric layer to form the spin-on dielectric material;
and polishing the dielectric layer to co-planarize top surfaces of the spin-on dielectric material, the gate capping structure, and the S/D contact structure.
‘482 discloses the method of claim 17 of the instant application, as shown above, but does not directly state the limitation, “wherein the dielectric structure is in contact with at least one of the sidewall gate capping structure and a sidewall of the S/D contact structure.” However, “depositing a dielectric layer in the recess,” wherein the recess was formed by, “etching a top portion of at least one of the first spacer layer,” which is in contact with the gate capping structure, “and the second spacer layer,” which is in contact with the S/D contact structure, results in a dielectric layer in contact with at least one of the sidewall gate capping structure and a sidewall of the S/D contact structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights