DUAL METAL CAPPED VIA CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES

Application No. 18/769,271

• Filed: Jul 10, 2024
• Priority: Nov 22, 2019 — continuation of 10/964,792
  • Mar 02, 2021 — divisional of 11/670,694
  • Apr 24, 2023 — continuation of 12/100,745
• Examiner: HARRISTON, WILLIAM A
• Art Unit: 2899
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
• OA Round: 1 (Non-Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Information Disclosure Statement
The information disclosure statements filed on 07/10/2024 have been considered.
Drawings
The drawings filed on 07/10/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 07/10/2024 are acceptable.

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

Claim(s) 10-19 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Pillarisetty (US 2015/0091067).

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Regarding claim10, Pillarisetty (US 2015/0091067) discloses:
A semiconductor device, comprising:
a transistor (¶0030) on a substrate (101, ¶0030), wherein the transistor comprises a source/drain (S/D) region (105, 106, ¶0036) and a gate structure (104, ¶0035);
a dielectric layer (107, ¶0046) on the transistor;
a device contact structure (109, ¶0056) extending through the dielectric layer (107) and connected to the S/D region (105); and
a via contact structure on the device contact structure, wherein the via contact structure comprises a via contact plug (110, ¶0057) interposed between a first metal capping layer (111, ¶0058) and a second metal capping layer (112, ¶0058), and
wherein the via contact plug (110, conductive oxide, ¶0054) has a material composition different from that of the first and second metal capping layers (metal, ¶0054).
Regarding claim 11, Pillarisetty further discloses:
wherein the first and second metal capping layers (111, 112) have a same material composition (¶0054).
Regarding claim 12, Pillarisetty further discloses:
further comprising an interconnect structure (113, ¶0057) on the via contact structure, wherein the interconnect structure has a material composition (metal, ¶0058) different from that of the via contact plug (110, conductive oxide).
Regarding claim 13, Pillarisetty further discloses:
wherein the via contact plug (110) has a material composition different from that of the device contact structure (109, metal, ¶0058).
Regarding claim 14, Pillarisetty further discloses:
wherein the S/D region (106) is connected to the via structure (110) via the device contact structure (109).
Regarding claim 15, Pillarisetty further discloses:
wherein the gate structure is connected to the via contact structure via the device contact structure.
Regarding claim 16, Pillarisetty further discloses:
A semiconductor device, comprising:
a transistor (¶0030) on a substrate (101);
a device contact structure (109) on the transistor;
a dielectric layer (107) on the device contact structure 9109); and
a via contact structure extending through the dielectric layer and connected to the device contact structure (109), wherein the via contact structure comprises a via contact plug (110) interposed between a first metal capping layer (111) and a second metal capping layer (112), and wherein the via contact plug (110) is in direct contact with the dielectric layer (107).
Regarding claim 17, Pillarisetty further discloses:
wherein the first and second metal capping layers (111, 113) have a same material composition (¶0054).
Regarding claim 18, Pillarisetty further discloses:
wherein the via contact plug (110) has a material composition (conductive oxide) different from that of the first and second metal capping layers (111, 113, metal).
Regarding claim 19, Pillarisetty further discloses:
wherein the device contact structure (109, metal) has a material composition different from that of the via contact plug (110, conductive oxide).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 20, the prior art does not disclose “an additional dielectric layer on the dielectric layer, wherein the via contact plug is within the dielectric layer and the additional dielectric layer” in combination with the remaining claimed features.
Claims 1-9 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art does not disclose “a second dielectric layer on the device contact structure; a first metal capping layer on the device contact structure and within the first and second dielectric layers, wherein the first metal capping layer comprises a first metal; and a via contact plug on the first metal capping layer, wherein the via contact plug comprises a second metal different from the first metal and the second metal is in direct contact with the second dielectric layer” in combination with the remaining claimed features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is [phone]. The examiner can normally be reached Mon-Fri, 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899

Prosecution Timeline

• Jul 10, 2024: Application Filed
• Sep 30, 2026: Non-Final Rejection mailed — §102, §Other (current)