DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 recites the limitation "the first/second conductive pillar" in lines 11-12 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner suggests changing “a bit/source line” to “a first/second conductive pillar” or vice versa to overcome the antecedent basis issue.
Claim 13 recites the limitation "the first conductive pillar" in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner suggest changing “the first/second conductive pillar” to “a first/second conductive pillar” or a statement consistent with claim 11 to overcome the antecedent basis issue.
Claim 14 recites the limitation "the first/second conductive pillar" in lines 2-3 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner suggest changing “the first/second conductive pillar” to “a first/second conductive pillar” or a statement consistent with claim 11 to overcome the antecedent basis issue.
Claim 15 recites the limitation "the first/second conductive pillar" in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner suggest changing “the first/second conductive pillar” to “a first/second conductive pillar” or a statement consistent with claim 11 to overcome the antecedent basis issue.
Claim 16 recites the limitation "the first/second conductive pillars" in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner suggest changing “the first/second conductive pillar” to “a first/second conductive pillar” or a statement consistent with claim 11 to overcome the antecedent basis issue.
Claim 17 recites the limitation "the data storage layer" in line 8 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner suggest changing “data storage” to “charge storage” to overcome the antecedent basis issue.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 9, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lue et al. (2020/0381450, hereafter Lue).
Regarding claim 1, Lue discloses a memory device, comprising: a multi-layer stack (10, Fig. 2E) disposed on a substrate (100, Fig. 2E, par. 0043) and comprising conductive layers (126, Fig. 2E) and dielectric layers (104, Fig. 2E) stacked alternately; a channel layer (112, Fig. 2E) penetrating through the multi-layer stack; a charge storage layer (110, Fig. 2E) disposed between the conductive layers and the channel layer; a first conductive pillar (122, Fig. 2E, 3) and a second conductive pillar (124, Fig. 2E, 3) adjacent to the channel layer; a first interconnect structure (306 upper, Fig. 3) connected to an end of the first conductive pillar; and a second interconnect structure (306 lower, Fig. 3) connected to an end of the second conductive pillar, wherein: the end of the first conductive pillar connected to the first interconnect structure and the end of the second conductive pillar connected to the second interconnect structure are located on opposite sides of the multi-layer stack (Fig. 3).
Regarding claim 2, Lue discloses a memory device wherein the first interconnect structure (306 upper, Fig. 3) and the second interconnect structure (306 lower, Fig. 3) respectively include a conductive line (par. 0057).
Regarding claim 9, Lue discloses a memory device further comprising: a dielectric pillar (116, Fig. 2E, par. 0046) enclosed by the channel layer (112, Fig. 2E).
Regarding claim 10, Lue discloses a memory device wherein the dielectric pillar (116) is in contact with the first and second conductive pillars (122/124) in a top view (Fig. 2E, 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lue in view of Jiang et al. (2021/0143170, hereafter Jiang).
Regarding claim 3, Lue fails to disclose a memory device wherein: the channel layer comprises a first channel portion and a second channel portion separated from each other, the first channel portion comprises a first end and a second end opposite to each other, the second channel portion comprises a third end and a fourth end opposite to each other, and the first conductive pillar is physically connected to the first end of the first channel portion and the third end of the second channel portion.
However, Jiang teaches a memory device wherein: the channel layer (106, Fig. 4B) comprises a first channel portion (106 left, Fig. 6A) and a second channel portion (106 right, Fig. 6A) separated from each other, the first channel portion comprises a first end and a second end opposite to each other, the second channel portion comprises a third end and a fourth end opposite to each other, and the first conductive pillar (601, Fig. 6A) is physically connected to the first end of the first channel portion and the third end of the second channel portion (Fig. 6A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing channel portions separated by a conductive pillar in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 4, Lue fails to disclose a memory device wherein the second conductive pillar is physically connected to the second end of the first channel portion and the fourth end of the second channel portion.
However, Jiang teaches a memory device wherein the second conductive pillar (602, Fig. 6A) is physically connected to the second end of the first channel portion (106 left, Fig. 6A) and the fourth end of the second channel portion (106 right, Fig. 6A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing channel portions separated by a conductive pillar in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 5, Lue fails to disclose a memory device wherein: the charge storage layer comprises a first charge storage portion and a second charge storage portion separated from each other, the first charge storage portion comprises a first end and a second end opposite to each other, the second charge storage portion comprises a third end and a fourth end opposite to each other, and the first conductive pillar is physically connected to the first end of the first charge storage portion and the third end of the second charge storage portion.
However, Jiang teaches a memory device wherein: the charge storage layer (105, Fig. 4B) comprises a first charge storage portion (105 left, Fig. 6A) and a second charge storage portion (105 right, Fig. 6A) separated from each other, the first charge storage portion comprises a first end and a second end opposite to each other, the second charge storage portion comprises a third end and a fourth end opposite to each other (Fig. 6A), and the first conductive pillar (601, Fig. 6A) is physically connected to the first end of the first charge storage portion and the third end of the second charge storage portion.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing storage portions separated by a conductive pillar in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 6, Lue fails to disclose a memory device wherein the second conductive pillar is physically connected to the second end of the first charge storage portion and the fourth end of the second charge storage portion.
However, Jiang teaches a memory device wherein the second conductive pillar (602, Fig. 6A) is physically connected to the second end of the first charge storage (105 left, Fig. 6A) portion and the fourth end of the second charge storage portion (105 right, Fig. 6A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing storage portions separated by a conductive pillar in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 17, Lue discloses a memory device, comprising: a multi-layer stack (10) disposed on a substrate (100) and comprising conductive layers (126) and dielectric layers (104) stacked alternately; a channel layer (112), a lengthwise direction of the channel layer being substantially perpendicular to a lengthwise direction of the multi-layer stack; a charge storage (110) layer disposed between the multi-layer stack and the channel layer; a first conductive pillar (122) and a second conductive pillar (124), a first interconnect line (306 left, Fig. 3) connected to the first conductive pillar; and a second interconnect line (306 right, Fig. 3) connected to the second conductive pillar.
Lue fails to disclose each of the first and second conductive pillars connecting the channel layer and the data storage layer in a top view.
However, Jiang teaches each of the first and second conductive pillars (601/602, Fig. 6A) connecting the channel layer (106, Fig. 4B, 6A) and the data storage layer (105, Fig. 4B, 6A) in a top view.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing conductive pillars connecting the channel and storage layers in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 18, Lue discloses a memory device wherein the first and second interconnect lines (306) are disposed at two opposing sides of the multi-layer stack (Fig. 3).
Regarding claim 20, Lue discloses a memory device further comprising: a dielectric pillar (116) enclosed by the channel layer (112) and separating the first conductive pillar (122) from the second conductive pillar (124) (Fig. 2E).
Claims 11, 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lue in view of Son et al. (2018/0019257, hereafter Son).
Regarding claim 11, Lue discloses a memory device, comprising: a multi-layer stack (10, Fig. 2E) disposed on a substrate (100, Fig. 2E) and comprising layers (126, Fig. 2E) and dielectric layers (104, Fig. 2E) stacked alternately, the layers being elongated in a first direction; a channel layer (112, Fig. 2E) penetrating through the multi-layer stack, the channel layer being elongated in a second direction substantially perpendicular to the first direction; a charge storage layer (110, Fig. 2E) disposed between the layers and the channel layer, the charge storage layer being elongated in the second direction; a bit line and a source line (122/124, Fig. 2E) being elongated in the second direction and separated from each other; a first interconnect line (306 upper, Fig. 3) connected to the first conductive pillar (122); and a second interconnect line (306 lower, Fig. 3) connected to the second conductive pillar (124), the first and second interconnect lines being elongated in the first direction.
Lue fails to disclose word line layers.
However, Son teaches word line layers (130, Fig. 4, par. 0063).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Son by providing layers that are word lines because they carry control voltages required to select specific rows of memory cells and apply necessary electric fields need to read/program/erase charge storage layers.
Regarding claim 12, Lue discloses a memory device wherein the first and second interconnect lines (306, Fig. 3) are disposed at two opposing sides of the multi-layer stack (Fig. 3).
Regarding claim 14, Lue discloses a memory device further comprising: a dielectric pillar (116) enclosed by the channel layer (112) and separating the first conductive pillar (122) from the second conductive pillar (124) (Fig. 2E).
Regarding claim 15, Lue discloses a memory device wherein lengthwise directions of the first conductive pillar (122), the second conductive pillar (124), and the dielectric pillar (116) are substantially perpendicular to the lengthwise direction of the multi-layer stack (10) (Fig. 2E).
Claims 7, 8, 13, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lue in view of Son and Jiang.
Regarding claim 7, Lue, discussed above, fails to disclose a memory device wherein the channel layer is separated from the charge storage layer by a first dielectric layer.
However, Son teaches a memory device wherein the channel layer (110, Fig. 6) is separated from the charge storage layer (164, Fig. 6) by a first dielectric layer (162, Fig. 6, par. 0068).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Son by providing a dielectric layer to separate the channel and storage layers in order to allow controlled carrier tunneling during write/erase operations while preventing unwanted charge leakage.
Lue and Son fail to disclose the first dielectric layer is in contact with the first and second conductive pillars in a top view.
However, Jiang teaches the first dielectric layer is in contact with the first and second conductive pillars (601/602, Fig. 6A) in a top view.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue and Son with Jiang by providing first and second pillars in contact with the dielectric layer in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 8, Lue fails to disclose a memory device wherein the multi-layer stack is separated from the charge storage layer by a second dielectric layer.
However, Son teaches a memory device wherein the multi-layer stack (144/133, Fig. 6) is separated from the charge storage layer (164, Fig. 6) by a second dielectric layer (166, Fig. 6, par. 0068).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Son by providing a dielectric layer to separate the storage layer and stack in order to prevent stored electrons from leaking out into conductive control gates during retention while blocking unwanted electron injection from gates into storage layer.
Lue and Son fail to disclose the second dielectric layer is in contact with the first and second conductive pillars in a top view.
However, Jiang teaches the second dielectric layer is in contact with the first and second conductive pillars (601/602, Fig. 6A) in a top view.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue and Son with Jiang by providing a dielectric layer in contact with conductive pillars in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 13, Lue fails to disclose a memory device wherein the first conductive pillar is in contact with the channel layer and the charge storage layer.
However, Jiang teaches a memory device wherein the first conductive pillar (601) is in contact with the channel layer (106) and the charge storage layer (105) (Fig. 6A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing a conductive pillar in contact with channel and storage layers in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 16, Lue fails to disclose a memory device wherein the first and second conductive pillars are in contact with the charge storage layer.
However, Jiang teaches a memory device wherein the first and second conductive pillars (601/602) are in contact with the charge storage layer (105) (Fig. 6A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Jiang by providing conductive pillars in contact with the storage layer in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
Regarding claim 19, Lue fails to disclose a memory device wherein the multi-layer stack is separated from the charge storage layer by a dielectric layer.
However, Son teaches a memory device wherein the multi-layer stack (144/133/143) is separated from the charge storage layer (164) by a dielectric layer (166) (Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue with Son by providing a dielectric layer to separate the stack from the storage layer in order to prevent stored electrons from leaking out into conductive control gates during retention while blocking unwanted electron injection from gates into storage layer.
Lue and Son fail to disclose the dielectric layer is in contact with the first and second conductive pillars in the top view.
However, Jiang teaches the dielectric layer is in contact with the first and second conductive pillars (601/602, Fig. 6A) in the top view.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lue and Son with Jiang by providing a dielectric layer in contact with conductive pillars in order to fill latency gap between DRAM type memory device and NAND flash type memory device, and optimizing density and operation speed of the memory device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Harari (20190319044), particularly with respect to claims 1, 12, and 18 pertaining to interconnects;
Song (20210327510), particularly pertaining to dielectric layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.M.B./ Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
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