DETAILED ACTION
The Amendment filed June 05, 2026 has been entered. Claims 1-20 are pending. Claims 1, 11 and 18 are independent.
Terminal Disclaimer
The terminal disclaimer filed on 06/05/2026 disclaiming the terminal portion of any patent granted on this application has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aoyama (US 5,335,199).
Regarding independent claim 1, Aoyama discloses a memory device, comprising:
a memory cell array (e.g., FIG. 9(a)-9(b)), having a plurality of memory cells (17), wherein each of the plurality of memory cells comprises a first port (e.g., BL2 pair) and a second port (BL4 pair);
a first control circuit (see EXMINER’S MARKUP below) arranged to electrically connect to the plurality of first ports;
a second control circuit (EXMINER’S MARKUP below) arranged to electrically connect to the plurality of first ports;
a third control circuit (EXMINER’S MARKUP below) arranged to electrically connect to the plurality of second ports;
a first pair of bit lines (BL2 pair) electrically connecting the first control circuit, the first port of each of the plurality of memory cells, and the second control circuit;
a second pair of bit lines (BL4 pair) electrically connecting the third control circuit and the second port of each of the plurality of memory cells; and
a first conductive line (EXMINER’S MARKUP below) electrically connecting the first control circuit and the second control circuit, wherein the first control circuit is configured to control the second control circuit via the first conductive line (i.e., connecting each row addresses and column addresses generated by address decoder) (see e.g., FIGS. 9(a)-9(b), and accompanying disclosure).
Regarding claim 2, which depends from claim 1, Aoyama discloses the memory device further comprises: a fourth control circuit (see EXMINER’S MARKUP below) arranged to electrically connect to the plurality of second ports, wherein the first control circuit and the second control circuit are disposed on opposite sides of the memory cell array, wherein the second control circuit is disposed between the memory cell array and the third control circuit, and the fourth control circuit is disposed between the memory cell array and the first control circuit (see e.g., FIGS 9(a)-9(b), and EXMINER’S MARKUP below)
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Regarding claims 3-4, which depends from claim 2, Aoyama discloses a second conductive line electrically connecting the third control circuit and the fourth control circuit, wherein the third control circuit is configured to control the fourth control circuit via the second conductive line; and the second pair of bit lines electrically connects the third control circuit, the second port of each of the plurality of memory cells, and the fourth control circuit (see e.g., FIGS 9(a)-9(b), and EXMINER’S MARKUP above).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Aoyama (US 5,335,199) in view of Ostermayr et al. (US 2012/0195151).
Regarding claim 5, Aoyama teaches the limitations of claim 1.
Aoyama is silent with respect to the first control circuit comprises: a first precharger, coupled to a first node of a first bit line of the first pair of bit lines and a first node of a second bit line of the first pair of bit lines, for precharging the first node of the first bit line and the first node of the second bit line during a reading operation of the memory device.
However, bit-line pre-charge circuit for a read cycle in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Ostermayr et al. (US 2012/0195151), FIG. 4 and accompanying disclosure, e.g., para. 0022: … charging BLA and BRA to VDD … with sense amplifier.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Ostermayr et al. to the teaching of Aoyama such that a memory, as taught by Aoyama, utilizes bit-line pre-charging, as taught by Ostermayr et al., for the purpose of enhancing memory access operations (see Ostermayr, para. 0022), further these conventional technology are well established in the art of the memory devices.
Regarding claims 6-7 and 12, Aoyama and Ostermayr et al., as combined teach the limitations of claims 5 and 11, respectively.
Ostermayr et al. further teach the second control circuit comprises: a second precharger, coupled to a second node of the first bit line and a second node of the second bit line, for precharging the second node of the first bit line and the second node of the second bit line during the reading operation of the memory device; and the first control circuit comprises: a first driver, coupled to the first node of the first bit line and the first node of the second bit line, for driving the first node of the first bit line and the first node of the second bit line during a writing operation of the memory device (see FIG. 4 and accompanying disclosure; further these conventional technology are well established in the art of the memory devices).
Regarding claims 8-10, 13 and 14-16, Aoyama and Ostermayr et al., as combined teach the limitations of claims 7, 12 and 11,, respectively.
Aoyama and Ostermayr are silent with respect to driver circuit during a memory operation and bit line equalizer circuit.
However, write driver and bit line equalizer circuit position in one side of memory array is a well-known technology for a type of memory circuit for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory used driver circuits positioned in one side of memory circuit because these conventional technology are well established in the art of the memory devices.
Regarding independent claim 11, Aoyama teaches a memory device, comprising: a memory cell array, having a plurality of memory cells, wherein each of the plurality of memory cells comprises a first connecting node, a second connecting node, a third connecting node, and a fourth connecting node; a first control circuit arranged to electrically connect to the plurality of first connecting nodes and second connecting nodes of the plurality of memory cells; and a second control circuit arranged to electrically connect to the plurality of first connecting nodes and second connecting nodes of the plurality of memory cells; a third control circuit arranged to electrically connect to the plurality of third connecting nodes and fourth connecting nodes of the plurality of memory cells; a fourth control circuit arranged to electrically connect to the plurality of third connecting nodes and fourth connecting nodes of the plurality of memory cells; a first bit line electrically connecting the first control circuit, the first connecting node, and the second control circuit; a second bit line electrically connecting the first control circuit, the second connecting node, and the second control circuit; a third bit line electrically connecting the third control circuit, the third connecting node, and the fourth control circuit; a fourth bit line electrically connecting the third control circuit, the fourth connecting node, and the fourth control circuit; and a first conductive line electrically connecting the first control circuit and the second control circuit, wherein the first control circuit is configured to control the second control circuit via the first conductive line (see e.g., FIGS 9(a)-9(b), and EXMINER’S MARKUP above).
Aoyama is silent with respect to the first control circuit comprises: a first precharger, coupled to a first node of the first bit line and a first node of the second bit line, for precharging the first node of the first bit line and the first node of the second bit line during a reading operation of the memory device.
However, bit-line pre-charge circuit for a read cycle in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Ostermayr et al. (US 2012/0195151), FIG. 4 and accompanying disclosure, e.g., para. 0022: … charging BLA and BRA to VDD … with sense amplifier.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Ostermayr et al. to the teaching of Aoyama such that a memory, as taught by Aoyama, utilizes bit-line pre-charging, as taught by Ostermayr et al., for the purpose of enhancing memory access operations (see Ostermayr, para. 0022), further these conventional technology are well established in the art of the memory devices.
Regarding claim 17, Aoyama and Ostermayr et al., as combined teach the limitations of claim 11.
Aoyama further teach a second conductive line electrically connecting the third control circuit and the fourth control circuit, wherein the third control circuit is configured to control the fourth control circuit via the second conductive line (see e.g., FIGS. 9(a)-(b), and accompanying disclosure).
Claims 18-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Aoyama (US 5,335,199) in view of e.g., Kuenemund et al. (US 2018/0218177).
Regarding independent claim 18, Aoyama teaches a memory cell array, having a plurality of memory cells, wherein each of the plurality of memory cells comprises a first connecting node, a second connecting node, a third connecting node, and a fourth connecting node; a first control circuit arranged to electrically connect to the plurality of first connecting nodes and second connecting nodes; a second control circuit arranged to electrically connect to the plurality of first connecting nodes and second connecting nodes; a third control circuit arranged to electrically connect to the plurality of third connecting nodes and fourth connecting nodes; a first bit line electrically connecting the first control circuit and the first connecting node of each of the plurality of memory cells; a second bit line electrically connecting the first control circuit and the second connecting node of each of the plurality of memory cells; a third bit line electrically connecting the third control circuit and the third connecting node of each of the plurality of memory cells; a fourth bit line electrically connecting the third control circuit and the fourth connecting node of each of the plurality of memory cells; a first conductive line electrically connecting the first control circuit and the second control circuit, wherein the first control circuit is configured to control the second control circuit via the first conductive line (see e.g., FIGS 9(a)-9(b), and EXMINER’S MARKUP above).
Aoyama is silent with respect to a latching circuit arranged to latch a voltage on one of the first bit line and the second bit line into a supply voltage level.
However, the claimed latching circuit in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Kuenemund et al. (US 2018/0218177), e.g., FIG. 1: 215, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Kuenemund et al. to the teaching of Aoyama such that a memory, as taught by Aoyama, utilizes keeper circuits, as taught by Kuenemund et al., for the purpose of keeping the bit line voltage to power voltage,thereby enhancing memory access operations, further these conventional technology are well established in the art of the memory devices.
Regarding claim 19, Aoyama and Kuenemund et al., as combined, teach the limitations of claim 18.
Aoyama further teaches the memory device further comprises: a fourth control circuit arranged to electrically connect to the plurality of third connecting nodes and fourth connecting nodes (see e.g., FIGS 9(a)-9(b), and EXMINER’S MARKUP above).
Regarding claim 20, Aoyama and Kuenemund et al., as combined, teach the limitations of claim 19.
Aoyama further teaches a second conductive line electrically connecting the third control circuit and the fourth control circuit, wherein the third control circuit is configured to control the fourth control circuit via the second conductive line (see e.g., FIGS 9(a)-9(b)).
Response to Arguments
Applicant’s arguments filed 06/05/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered but are not persuasive.
Applicant argues that Aoyama fails to teach or suggest the features “the first control circuit is configured to control the second control circuit via the first conductive line”.
In response to the Applicant’s argument, as the applicant acknowledged, Aoyama’s a short-circuit transistor (claimed a first control circuit) provides shorting bit lines between the control circuit section connected to the top of the bit lines and the control circuit section connected to the bottom side of the bit lines. For example, short-circuiting the bit lines between BL2 and BL3 in the EXMINER’S MARKUP shown above.
Here, BL2 is connected to a pass-transistor (claimed a second control circuit) controlled by the column selection signal Y2 (claimed a first conductive line), and BL3 is connected to a pass-transistor controlled by the column selection signal Y3 (claimed a first conductive line).
Aoyama’s a multiport memory allows simultaneous reading and/or writing to the same memory cells by shorting selected bit line with other bit lines of cells. When shorting the selected bit line to the other bit line of the cell, the column selection transistors are turned on simultaneously (in which case Y2 and Y3 are turned on simultaneously). Of course, if there is no need to short the selected bit with the bit line of another cell, the Aoyama’s memory performs memory operations (in which case Y2 and Y3 are turned on separately).
Referring to Aoyama, column 9, line 61 through column 10, line8; and column 6, lines 12-33.
In other words, the on/off state of pass-transistor (claimed a second control circuit) is determined as the short-circuit transistor (claimed a first control circuit) is activated or deactivated via the column selection signal (claimed a first conductive line).
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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